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https://github.com/brain-hackers/u-boot-brain
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1a4596601f
Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
130 lines
3.0 KiB
C
130 lines
3.0 KiB
C
/*
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* (C) Copyright 2006
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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struct pdnb3_ndfc_regs {
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uchar cmd;
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uchar wait;
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uchar addr;
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uchar term;
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uchar data;
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};
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static u8 hwctl;
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static struct pdnb3_ndfc_regs *pdnb3_ndfc;
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#define readb(addr) *(volatile u_char *)(addr)
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#define readl(addr) *(volatile u_long *)(addr)
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#define writeb(d,addr) *(volatile u_char *)(addr) = (d)
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/*
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* The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to
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* the NAND devices. The NDFC has command, address and data registers that
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* when accessed will set up the NAND flash pins appropriately. We'll use the
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* hwcontrol function to save the configuration in a global variable.
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* We can then use this information in the read and write functions to
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* determine which NDFC register to access.
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*
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* There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte).
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*/
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static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtd->priv;
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if (ctrl & NAND_CTRL_CHANGE) {
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if ( ctrl & NAND_CLE )
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hwctl |= 0x1;
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else
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hwctl &= ~0x1;
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if ( ctrl & NAND_ALE )
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hwctl |= 0x2;
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else
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hwctl &= ~0x2;
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if ( (ctrl & NAND_NCE) != NAND_NCE)
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writeb(0x00, &(pdnb3_ndfc->term));
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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static u_char pdnb3_nand_read_byte(struct mtd_info *mtd)
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{
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return readb(&(pdnb3_ndfc->data));
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}
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static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++) {
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if (hwctl & 0x1)
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writeb(buf[i], &(pdnb3_ndfc->cmd));
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else if (hwctl & 0x2)
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writeb(buf[i], &(pdnb3_ndfc->addr));
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else
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writeb(buf[i], &(pdnb3_ndfc->data));
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}
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}
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static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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buf[i] = readb(&(pdnb3_ndfc->data));
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}
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static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len)
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{
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int i;
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for (i = 0; i < len; i++)
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if (buf[i] != readb(&(pdnb3_ndfc->data)))
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return i;
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return 0;
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}
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static int pdnb3_nand_dev_ready(struct mtd_info *mtd)
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{
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/*
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* Blocking read to wait for NAND to be ready
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*/
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readb(&(pdnb3_ndfc->wait));
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/*
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* Return always true
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*/
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return 1;
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}
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int board_nand_init(struct nand_chip *nand)
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{
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pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
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nand->ecc.mode = NAND_ECC_SOFT;
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/* Set address of NAND IO lines (Using Linear Data Access Region) */
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nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
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nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4);
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/* Reference hardware control function */
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nand->cmd_ctrl = pdnb3_nand_hwcontrol;
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nand->read_byte = pdnb3_nand_read_byte;
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nand->write_buf = pdnb3_nand_write_buf;
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nand->read_buf = pdnb3_nand_read_buf;
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nand->verify_buf = pdnb3_nand_verify_buf;
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nand->dev_ready = pdnb3_nand_dev_ready;
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return 0;
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}
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#endif
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