mirror of
https://github.com/brain-hackers/u-boot-brain
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46263f2de4
This commit adapts the files that were derived from PIBS (PowerPC Initialization and Boot Software) codeto using SPDX License Identifiers. So far, SPDX has not assigned an official License ID for the PIBS license yet, so this should be considered preliminary. Note that the following files contained incorrect license information: arch/powerpc/cpu/ppc4xx/4xx_uart.c arch/powerpc/cpu/ppc4xx/start.S arch/powerpc/include/asm/ppc440.h These files included, in addition to the GPL-2.0 / ibm-pibs dual license as inherited from PIBS, a GPL-2.0+ license header which was obviously incorrect. This has been removed. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de> Conflicts: Licenses/README Acked-by: Stefan Roese <sr@denx.de>
195 lines
6.1 KiB
ArmAsm
195 lines
6.1 KiB
ArmAsm
/*
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* SPDX-License-Identifier: GPL-2.0 ibm-pibs
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*/
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#include <config.h>
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#include <asm/ppc4xx.h>
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#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#define LI32(reg,val) \
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addis reg,0,val@h;\
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ori reg,reg,val@l
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#define WDCR_EBC(reg,val) \
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addi r4,0,reg;\
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mtdcr EBC0_CFGADDR,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr EBC0_CFGDATA,r4
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#define WDCR_SDRAM(reg,val) \
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addi r4,0,reg;\
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mtdcr SDRAM0_CFGADDR,r4;\
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addis r4,0,val@h;\
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ori r4,r4,val@l;\
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mtdcr SDRAM0_CFGDATA,r4
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/******************************************************************************
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* Function: ext_bus_cntlr_init
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*
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* Description: Configures EBC Controller and a few basic chip selects.
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*
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* CS0 is setup to get the Boot Flash out of the addresss range
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* so that we may setup a stack. CS7 is setup so that we can
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* access and reset the hardware watchdog.
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*
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* IMPORTANT: For pass1 this code must run from
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* cache since you can not reliably change a peripheral banks
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* timing register (pbxap) while running code from that bank.
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* For ex., since we are running from ROM on bank 0, we can NOT
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* execute the code that modifies bank 0 timings from ROM, so
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* we run it from cache.
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*
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* Notes: Does NOT use the stack.
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*****************************************************************************/
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.section ".text"
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.align 2
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.globl ext_bus_cntlr_init
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.type ext_bus_cntlr_init, @function
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ext_bus_cntlr_init:
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mflr r0
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/********************************************************************
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* Prefetch entire ext_bus_cntrl_init function into the icache.
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* This is necessary because we are going to change the same CS we
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* are executing from. Otherwise a CPU lockup may occur.
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*******************************************************************/
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bl ..getAddr
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..getAddr:
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mflr r3 /* get address of ..getAddr */
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/* Calculate number of cache lines for this function */
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addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
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mtctr r4
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..ebcloop:
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icbt r0, r3 /* prefetch cache line for addr in r3*/
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addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
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bdnz ..ebcloop /* continue for $CTR cache lines */
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/********************************************************************
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* Delay to ensure all accesses to ROM are complete before changing
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* bank 0 timings. 200usec should be enough.
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
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*******************************************************************/
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addis r3, 0, 0x0
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ori r3, r3, 0xA000 /* wait 200us from reset */
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mtctr r3
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..spinlp:
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bdnz ..spinlp /* spin loop */
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/********************************************************************
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* SETUP CPC0_CR0
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*******************************************************************/
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LI32(r4, 0x00c01030)
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mtdcr CPC0_CR0, r4
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/********************************************************************
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* Setup CPC0_CR1: Change PCIINT signal to PerWE
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*******************************************************************/
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mfdcr r4, CPC0_CR1
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ori r4, r4, 0x4000
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mtdcr CPC0_CR1, r4
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/********************************************************************
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* Setup External Bus Controller (EBC).
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*******************************************************************/
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WDCR_EBC(EBC0_CFG, 0xd84c0000)
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/********************************************************************
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* Memory Bank 0 (Intel 28F640J3 Flash) initialization
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*******************************************************************/
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/*WDCR_EBC(PB1AP, 0x03055200)*/
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/*WDCR_EBC(PB1AP, 0x04055200)*/
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WDCR_EBC(PB1AP, 0x08055200)
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WDCR_EBC(PB0CR, 0xff87a000)
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/********************************************************************
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* Memory Bank 3 (Xilinx XC95144 CPLD) initialization
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*******************************************************************/
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/*WDCR_EBC(PB3AP, 0x07869200)*/
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WDCR_EBC(PB3AP, 0x04055200)
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WDCR_EBC(PB3CR, 0xf081c000)
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/********************************************************************
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* Memory Bank 1,2,4-7 (Unused) initialization
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*******************************************************************/
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WDCR_EBC(PB1AP, 0)
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WDCR_EBC(PB1CR, 0)
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WDCR_EBC(PB2AP, 0)
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WDCR_EBC(PB2CR, 0)
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WDCR_EBC(PB4AP, 0)
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WDCR_EBC(PB4CR, 0)
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WDCR_EBC(PB5AP, 0)
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WDCR_EBC(PB5CR, 0)
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WDCR_EBC(PB6AP, 0)
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WDCR_EBC(PB6CR, 0)
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WDCR_EBC(PB7AP, 0)
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WDCR_EBC(PB7CR, 0)
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/* We are all done */
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mtlr r0 /* Restore link register */
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blr /* Return to calling function */
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.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
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/* end ext_bus_cntlr_init() */
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/******************************************************************************
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* Function: sdram_init
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*
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* Description: Configures SDRAM memory banks.
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*
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* Notes: Does NOT use the stack.
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*****************************************************************************/
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.section ".text"
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.align 2
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.globl sdram_init
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.type sdram_init, @function
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sdram_init:
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/*
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* Disable memory controller to allow
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* values to be changed.
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*/
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WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
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/*
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* Configure Memory Banks
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*/
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WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
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WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
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WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
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WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
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/*
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* Set up SDTR1 (SDRAM Timing Register)
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*/
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WDCR_SDRAM(SDRAM0_TR, 0x00854009)
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/*
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* Set RTR (Refresh Timing Register)
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*/
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WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
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/* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
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/********************************************************************
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* Delay to ensure 200usec have elapsed since reset. Assume worst
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* case that the core is running 200Mhz:
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* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
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*******************************************************************/
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addis r3, 0, 0x0000
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ori r3, r3, 0xA000 /* Wait >200us from reset */
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mtctr r3
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..spinlp2:
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bdnz ..spinlp2 /* spin loop */
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/********************************************************************
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* Set memory controller options reg, MCOPT1.
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*******************************************************************/
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WDCR_SDRAM(SDRAM0_CFG,0x80800000)
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..sdri_done:
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blr /* Return to calling function */
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.Lfe1: .size sdram_init,.Lfe1-sdram_init
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/* end sdram_init() */
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