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https://github.com/brain-hackers/u-boot-brain
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5e2400e8f8
We can write the configuration table in last_stage_init() for all x86 boards, but not with coreboot since coreboot already has them. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
50 lines
1.4 KiB
C
50 lines
1.4 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_TABLES_H_
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#define _X86_TABLES_H_
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/*
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* All x86 tables happen to like the address range from 0xf0000 to 0x100000.
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* We use 0xf0000 as the starting address to store those tables, including
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* PIRQ routing table, Multi-Processor table and ACPI table.
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*/
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#define ROM_TABLE_ADDR 0xf0000
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/**
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* table_compute_checksum() - Compute a table checksum
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*
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* This computes an 8-bit checksum for the configuration table.
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* All bytes in the configuration table, including checksum itself and
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* reserved bytes must add up to zero.
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*
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* @v: configuration table base address
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* @len: configuration table size
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* @return: the 8-bit checksum
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*/
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u8 table_compute_checksum(void *v, int len);
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/**
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* write_tables() - Write x86 configuration tables
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*
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* This writes x86 configuration tables, including PIRQ routing table,
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* Multi-Processor table and ACPI table. Whether a specific type of
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* configuration table is written is controlled by a Kconfig option.
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*/
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void write_tables(void);
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/**
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* write_pirq_routing_table() - Write PIRQ routing table
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*
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* This writes PIRQ routing table at a given address.
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*
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* @start: start address to write PIRQ routing table
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* @return: end address of PIRQ routing table
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*/
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u32 write_pirq_routing_table(u32 start);
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#endif /* _X86_TABLES_H_ */
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