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https://github.com/brain-hackers/u-boot-brain
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a2f5d091cc
Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
39 lines
942 B
C
39 lines
942 B
C
/*
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* From coreboot file of the same name
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*
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* Copyright (C) 2010 coresystems GmbH
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __ASM_IOAPIC_H
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#define __ASM_IOAPIC_H
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#define IO_APIC_ADDR 0xfec00000
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#define IO_APIC_INDEX IO_APIC_ADDR
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#define IO_APIC_DATA (IO_APIC_ADDR + 0x10)
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#define IO_APIC_INTERRUPTS 24
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#define ALL (0xff << 24)
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#define NONE 0
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#define DISABLED (1 << 16)
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#define ENABLED (0 << 16)
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#define TRIGGER_EDGE (0 << 15)
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#define TRIGGER_LEVEL (1 << 15)
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#define POLARITY_HIGH (0 << 13)
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#define POLARITY_LOW (1 << 13)
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#define PHYSICAL_DEST (0 << 11)
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#define LOGICAL_DEST (1 << 11)
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#define ExtINT (7 << 8)
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#define NMI (4 << 8)
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#define SMI (2 << 8)
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#define INT (1 << 8)
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u32 io_apic_read(u32 ioapic_base, u32 reg);
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void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
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void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
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void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
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void clear_ioapic(u32 ioapic_base);
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#endif
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