730 lines
15 KiB
C
730 lines
15 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* (C) Copyright 2014 - 2015 Xilinx, Inc.
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* Michal Simek <michal.simek@xilinx.com>
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*/
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#include <common.h>
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#include <command.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <env.h>
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#include <env_internal.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <sata.h>
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#include <ahci.h>
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#include <scsi.h>
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#include <malloc.h>
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#include <wdt.h>
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#include <asm/arch/clk.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/psu_init_gpl.h>
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#include <asm/cache.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/ptrace.h>
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#include <dm/device.h>
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#include <dm/uclass.h>
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#include <usb.h>
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#include <dwc3-uboot.h>
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#include <zynqmppl.h>
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#include <zynqmp_firmware.h>
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#include <g_dnl.h>
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#include <linux/bitops.h>
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#include <linux/delay.h>
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#include <linux/sizes.h>
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#include "../common/board.h"
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#include "pm_cfg_obj.h"
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#define ZYNQMP_VERSION_SIZE 7
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#define EFUSE_VCU_DIS_MASK 0x100
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#define EFUSE_VCU_DIS_SHIFT 8
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#define EFUSE_GPU_DIS_MASK 0x20
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#define EFUSE_GPU_DIS_SHIFT 5
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#define IDCODE2_PL_INIT_MASK 0x200
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#define IDCODE2_PL_INIT_SHIFT 9
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DECLARE_GLOBAL_DATA_PTR;
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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static xilinx_desc zynqmppl = XILINX_ZYNQMP_DESC;
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enum {
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ZYNQMP_VARIANT_EG = BIT(0U),
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ZYNQMP_VARIANT_EV = BIT(1U),
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ZYNQMP_VARIANT_CG = BIT(2U),
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ZYNQMP_VARIANT_DR = BIT(3U),
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};
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static const struct {
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u32 id;
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u8 device;
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u8 variants;
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} zynqmp_devices[] = {
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{
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.id = 0x04711093,
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.device = 2,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04710093,
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.device = 3,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04721093,
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.device = 4,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04720093,
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.device = 5,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04739093,
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.device = 6,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04730093,
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.device = 7,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG |
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ZYNQMP_VARIANT_EV,
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},
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{
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.id = 0x04738093,
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.device = 9,
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.variants = ZYNQMP_VARIANT_EG | ZYNQMP_VARIANT_CG,
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},
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{
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.id = 0x04740093,
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.device = 11,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04750093,
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.device = 15,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04759093,
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.device = 17,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x04758093,
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.device = 19,
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.variants = ZYNQMP_VARIANT_EG,
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},
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{
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.id = 0x047E1093,
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.device = 21,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E3093,
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.device = 23,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E5093,
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.device = 25,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E4093,
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.device = 27,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E0093,
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.device = 28,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E2093,
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.device = 29,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047E6093,
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.device = 39,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FD093,
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.device = 43,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047F8093,
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.device = 46,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FF093,
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.device = 47,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FB093,
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.device = 48,
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.variants = ZYNQMP_VARIANT_DR,
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},
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{
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.id = 0x047FE093,
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.device = 49,
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.variants = ZYNQMP_VARIANT_DR,
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},
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};
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static char *zynqmp_get_silicon_idcode_name(void)
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{
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u32 i;
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u32 idcode, idcode2;
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char name[ZYNQMP_VERSION_SIZE];
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u32 ret_payload[PAYLOAD_ARG_CNT];
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int ret;
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ret = xilinx_pm_request(PM_GET_CHIPID, 0, 0, 0, 0, ret_payload);
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if (ret) {
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debug("%s: Getting chipid failed\n", __func__);
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return "unknown";
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}
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/*
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* Firmware returns:
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* payload[0][31:0] = status of the operation
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* payload[1]] = IDCODE
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* payload[2][19:0] = Version
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* payload[2][28:20] = EXTENDED_IDCODE
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* payload[2][29] = PL_INIT
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*/
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idcode = ret_payload[1];
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idcode2 = ret_payload[2] >> ZYNQMP_CSU_VERSION_EMPTY_SHIFT;
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debug("%s, IDCODE: 0x%0x, IDCODE2: 0x%0x\r\n", __func__, idcode,
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idcode2);
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for (i = 0; i < ARRAY_SIZE(zynqmp_devices); i++) {
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if (zynqmp_devices[i].id == (idcode & 0x0FFFFFFF))
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break;
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}
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if (i >= ARRAY_SIZE(zynqmp_devices))
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return "unknown";
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/* Add device prefix to the name */
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ret = snprintf(name, ZYNQMP_VERSION_SIZE, "zu%d",
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zynqmp_devices[i].device);
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if (ret < 0)
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return "unknown";
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if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EV) {
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/* Devices with EV variant might be EG/CG/EV family */
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if (idcode2 & IDCODE2_PL_INIT_MASK) {
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u32 family = ((idcode2 & EFUSE_VCU_DIS_MASK) >>
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EFUSE_VCU_DIS_SHIFT) << 1 |
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((idcode2 & EFUSE_GPU_DIS_MASK) >>
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EFUSE_GPU_DIS_SHIFT);
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/*
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* Get family name based on extended idcode values as
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* determined on UG1087, EXTENDED_IDCODE register
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* description
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*/
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switch (family) {
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case 0x00:
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strncat(name, "ev", 2);
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break;
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case 0x10:
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strncat(name, "eg", 2);
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break;
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case 0x11:
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strncat(name, "cg", 2);
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break;
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default:
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/* Do not append family name*/
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break;
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}
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} else {
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/*
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* When PL powered down the VCU Disable efuse cannot be
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* read. So, ignore the bit and just findout if it is CG
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* or EG/EV variant.
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*/
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strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" :
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"e", 2);
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}
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} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_CG) {
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/* Devices with CG variant might be EG or CG family */
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strncat(name, (idcode2 & EFUSE_GPU_DIS_MASK) ? "cg" : "eg", 2);
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} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_EG) {
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strncat(name, "eg", 2);
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} else if (zynqmp_devices[i].variants & ZYNQMP_VARIANT_DR) {
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strncat(name, "dr", 2);
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} else {
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debug("Variant not identified\n");
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}
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return strdup(name);
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}
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#endif
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int board_early_init_f(void)
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{
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#if defined(CONFIG_ZYNQMP_PSU_INIT_ENABLED)
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int ret;
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ret = psu_init();
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if (ret)
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return ret;
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/*
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* PS_SYSMON_ANALOG_BUS register determines mapping between SysMon
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* supply sense channel to SysMon supply registers inside the IP.
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* This register must be programmed to complete SysMon IP
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* configuration. The default register configuration after
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* power-up is incorrect. Hence, fix this by writing the
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* correct value - 0x3210.
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*/
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writel(ZYNQMP_PS_SYSMON_ANALOG_BUS_VAL,
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ZYNQMP_AMS_PS_SYSMON_ANALOG_BUS);
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/* Delay is required for clocks to be propagated */
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udelay(1000000);
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#endif
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#ifdef CONFIG_DEBUG_UART
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/* Uart debug for sure */
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debug_uart_init();
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puts("Debug uart enabled\n"); /* or printch() */
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#endif
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return 0;
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}
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static int multi_boot(void)
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{
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u32 multiboot;
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multiboot = readl(&csu_base->multi_boot);
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printf("Multiboot:\t%d\n", multiboot);
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return 0;
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}
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#define PS_SYSMON_ANALOG_BUS_VAL 0x3210
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#define PS_SYSMON_ANALOG_BUS_REG 0xFFA50914
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int board_init(void)
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{
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#if defined(CONFIG_ZYNQMP_FIRMWARE)
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struct udevice *dev;
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uclass_get_device_by_name(UCLASS_FIRMWARE, "zynqmp-power", &dev);
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if (!dev)
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panic("PMU Firmware device not found - Enable it");
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#endif
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#if defined(CONFIG_SPL_BUILD)
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/* Check *at build time* if the filename is an non-empty string */
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if (sizeof(CONFIG_ZYNQMP_SPL_PM_CFG_OBJ_FILE) > 1)
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zynqmp_pmufw_load_config_object(zynqmp_pm_cfg_obj,
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zynqmp_pm_cfg_obj_size);
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printf("Silicon version:\t%d\n", zynqmp_get_silicon_version());
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#else
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if (CONFIG_IS_ENABLED(DM_I2C) && CONFIG_IS_ENABLED(I2C_EEPROM))
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xilinx_read_eeprom();
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#endif
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printf("EL Level:\tEL%d\n", current_el());
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/* Bug in ROM sets wrong value in this register */
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writel(PS_SYSMON_ANALOG_BUS_VAL, PS_SYSMON_ANALOG_BUS_REG);
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#if CONFIG_IS_ENABLED(FPGA) && defined(CONFIG_FPGA_ZYNQMPPL)
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zynqmppl.name = zynqmp_get_silicon_idcode_name();
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printf("Chip ID:\t%s\n", zynqmppl.name);
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fpga_init();
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fpga_add(fpga_xilinx, &zynqmppl);
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#endif
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if (current_el() == 3)
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multi_boot();
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return 0;
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}
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int board_early_init_r(void)
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{
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u32 val;
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if (current_el() != 3)
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return 0;
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val &= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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if (!val) {
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val = readl(&crlapb_base->timestamp_ref_ctrl);
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val |= ZYNQMP_CRL_APB_TIMESTAMP_REF_CTRL_CLKACT;
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writel(val, &crlapb_base->timestamp_ref_ctrl);
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/* Program freq register in System counter */
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writel(zynqmp_get_system_timer_freq(),
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&iou_scntr_secure->base_frequency_id_register);
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/* And enable system counter */
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writel(ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN,
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&iou_scntr_secure->counter_control_register);
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}
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return 0;
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}
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unsigned long do_go_exec(ulong (*entry)(int, char * const []), int argc,
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char *const argv[])
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{
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int ret = 0;
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if (current_el() > 1) {
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smp_kick_all_cpus();
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dcache_disable();
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armv8_switch_to_el1(0x0, 0, 0, 0, (unsigned long)entry,
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ES_TO_AARCH64);
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} else {
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printf("FAIL: current EL is not above EL1\n");
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ret = EINVAL;
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}
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return ret;
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}
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#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
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int dram_init_banksize(void)
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{
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int ret;
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ret = fdtdec_setup_memory_banksize();
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if (ret)
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return ret;
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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if (fdtdec_setup_mem_size_base() != 0)
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return -EINVAL;
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return 0;
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}
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#else
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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mem_map_fill();
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return 0;
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}
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int dram_init(void)
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{
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gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
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CONFIG_SYS_SDRAM_SIZE);
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return 0;
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}
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#endif
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void reset_cpu(void)
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{
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}
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static u8 __maybe_unused zynqmp_get_bootmode(void)
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{
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u8 bootmode;
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u32 reg = 0;
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int ret;
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ret = zynqmp_mmio_read((ulong)&crlapb_base->boot_mode, ®);
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if (ret)
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return -EINVAL;
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if (reg >> BOOT_MODE_ALT_SHIFT)
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reg >>= BOOT_MODE_ALT_SHIFT;
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bootmode = reg & BOOT_MODES_MASK;
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return bootmode;
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}
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#if defined(CONFIG_BOARD_LATE_INIT)
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static const struct {
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u32 bit;
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const char *name;
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} reset_reasons[] = {
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{ RESET_REASON_DEBUG_SYS, "DEBUG" },
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{ RESET_REASON_SOFT, "SOFT" },
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{ RESET_REASON_SRST, "SRST" },
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{ RESET_REASON_PSONLY, "PS-ONLY" },
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{ RESET_REASON_PMU, "PMU" },
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{ RESET_REASON_INTERNAL, "INTERNAL" },
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{ RESET_REASON_EXTERNAL, "EXTERNAL" },
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{}
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};
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static int reset_reason(void)
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{
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u32 reg;
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int i, ret;
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const char *reason = NULL;
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ret = zynqmp_mmio_read((ulong)&crlapb_base->reset_reason, ®);
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if (ret)
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return -EINVAL;
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puts("Reset reason:\t");
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for (i = 0; i < ARRAY_SIZE(reset_reasons); i++) {
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if (reg & reset_reasons[i].bit) {
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reason = reset_reasons[i].name;
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printf("%s ", reset_reasons[i].name);
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break;
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}
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}
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puts("\n");
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env_set("reset_reason", reason);
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return 0;
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}
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static int set_fdtfile(void)
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{
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char *compatible, *fdtfile;
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const char *suffix = ".dtb";
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const char *vendor = "xilinx/";
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int fdt_compat_len;
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if (env_get("fdtfile"))
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return 0;
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compatible = (char *)fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (compatible && fdt_compat_len) {
|
|
char *name;
|
|
|
|
debug("Compatible: %s\n", compatible);
|
|
|
|
name = strchr(compatible, ',');
|
|
if (!name)
|
|
return -EINVAL;
|
|
|
|
name++;
|
|
|
|
fdtfile = calloc(1, strlen(vendor) + strlen(name) +
|
|
strlen(suffix) + 1);
|
|
if (!fdtfile)
|
|
return -ENOMEM;
|
|
|
|
sprintf(fdtfile, "%s%s%s", vendor, name, suffix);
|
|
|
|
env_set("fdtfile", fdtfile);
|
|
free(fdtfile);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
u8 bootmode;
|
|
struct udevice *dev;
|
|
int bootseq = -1;
|
|
int bootseq_len = 0;
|
|
int env_targets_len = 0;
|
|
const char *mode;
|
|
char *new_targets;
|
|
char *env_targets;
|
|
int ret;
|
|
|
|
#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_USB_GADGET_DOWNLOAD)
|
|
usb_ether_init();
|
|
#endif
|
|
|
|
if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
|
|
debug("Saved variables - Skipping\n");
|
|
return 0;
|
|
}
|
|
|
|
if (!CONFIG_IS_ENABLED(ENV_VARS_UBOOT_RUNTIME_CONFIG))
|
|
return 0;
|
|
|
|
ret = set_fdtfile();
|
|
if (ret)
|
|
return ret;
|
|
|
|
bootmode = zynqmp_get_bootmode();
|
|
|
|
puts("Bootmode: ");
|
|
switch (bootmode) {
|
|
case USB_MODE:
|
|
puts("USB_MODE\n");
|
|
mode = "usb_dfu0 usb_dfu1";
|
|
env_set("modeboot", "usb_dfu_spl");
|
|
break;
|
|
case JTAG_MODE:
|
|
puts("JTAG_MODE\n");
|
|
mode = "jtag pxe dhcp";
|
|
env_set("modeboot", "jtagboot");
|
|
break;
|
|
case QSPI_MODE_24BIT:
|
|
case QSPI_MODE_32BIT:
|
|
mode = "qspi0";
|
|
puts("QSPI_MODE\n");
|
|
env_set("modeboot", "qspiboot");
|
|
break;
|
|
case EMMC_MODE:
|
|
puts("EMMC_MODE\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff160000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff160000", &dev)) {
|
|
puts("Boot from EMMC but without SD0 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
|
|
|
|
mode = "mmc";
|
|
bootseq = dev_seq(dev);
|
|
break;
|
|
case SD_MODE:
|
|
puts("SD_MODE\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff160000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff160000", &dev)) {
|
|
puts("Boot from SD0 but without SD0 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc0 device found at %p, seq %d\n", dev, dev_seq(dev));
|
|
|
|
mode = "mmc";
|
|
bootseq = dev_seq(dev);
|
|
env_set("modeboot", "sdboot");
|
|
break;
|
|
case SD1_LSHFT_MODE:
|
|
puts("LVL_SHFT_");
|
|
/* fall through */
|
|
case SD_MODE1:
|
|
puts("SD_MODE1\n");
|
|
if (uclass_get_device_by_name(UCLASS_MMC,
|
|
"mmc@ff170000", &dev) &&
|
|
uclass_get_device_by_name(UCLASS_MMC,
|
|
"sdhci@ff170000", &dev)) {
|
|
puts("Boot from SD1 but without SD1 enabled!\n");
|
|
return -1;
|
|
}
|
|
debug("mmc1 device found at %p, seq %d\n", dev, dev_seq(dev));
|
|
|
|
mode = "mmc";
|
|
bootseq = dev_seq(dev);
|
|
env_set("modeboot", "sdboot");
|
|
break;
|
|
case NAND_MODE:
|
|
puts("NAND_MODE\n");
|
|
mode = "nand0";
|
|
env_set("modeboot", "nandboot");
|
|
break;
|
|
default:
|
|
mode = "";
|
|
printf("Invalid Boot Mode:0x%x\n", bootmode);
|
|
break;
|
|
}
|
|
|
|
if (bootseq >= 0) {
|
|
bootseq_len = snprintf(NULL, 0, "%i", bootseq);
|
|
debug("Bootseq len: %x\n", bootseq_len);
|
|
env_set_hex("bootseq", bootseq);
|
|
}
|
|
|
|
/*
|
|
* One terminating char + one byte for space between mode
|
|
* and default boot_targets
|
|
*/
|
|
env_targets = env_get("boot_targets");
|
|
if (env_targets)
|
|
env_targets_len = strlen(env_targets);
|
|
|
|
new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
|
|
bootseq_len);
|
|
if (!new_targets)
|
|
return -ENOMEM;
|
|
|
|
if (bootseq >= 0)
|
|
sprintf(new_targets, "%s%x %s", mode, bootseq,
|
|
env_targets ? env_targets : "");
|
|
else
|
|
sprintf(new_targets, "%s %s", mode,
|
|
env_targets ? env_targets : "");
|
|
|
|
env_set("boot_targets", new_targets);
|
|
|
|
reset_reason();
|
|
|
|
return board_late_init_xilinx();
|
|
}
|
|
#endif
|
|
|
|
int checkboard(void)
|
|
{
|
|
puts("Board: Xilinx ZynqMP\n");
|
|
return 0;
|
|
}
|
|
|
|
enum env_location env_get_location(enum env_operation op, int prio)
|
|
{
|
|
u32 bootmode = zynqmp_get_bootmode();
|
|
|
|
if (prio)
|
|
return ENVL_UNKNOWN;
|
|
|
|
switch (bootmode) {
|
|
case EMMC_MODE:
|
|
case SD_MODE:
|
|
case SD1_LSHFT_MODE:
|
|
case SD_MODE1:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_FAT))
|
|
return ENVL_FAT;
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_EXT4))
|
|
return ENVL_EXT4;
|
|
return ENVL_UNKNOWN;
|
|
case NAND_MODE:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_NAND))
|
|
return ENVL_NAND;
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_UBI))
|
|
return ENVL_UBI;
|
|
return ENVL_UNKNOWN;
|
|
case QSPI_MODE_24BIT:
|
|
case QSPI_MODE_32BIT:
|
|
if (IS_ENABLED(CONFIG_ENV_IS_IN_SPI_FLASH))
|
|
return ENVL_SPI_FLASH;
|
|
return ENVL_UNKNOWN;
|
|
case JTAG_MODE:
|
|
default:
|
|
return ENVL_NOWHERE;
|
|
}
|
|
}
|