mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
172 lines
4.3 KiB
C
172 lines
4.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* FlexBus Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __FLEXBUS_H
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#define __FLEXBUS_H
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/*********************************************************************
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* FlexBus Chip Selects (FBCS)
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*********************************************************************/
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#ifdef CONFIG_M5235
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typedef struct fbcs {
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u16 csar0; /* Chip-select Address */
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u16 res1;
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u32 csmr0; /* Chip-select Mask */
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u16 res2;
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u16 cscr0; /* Chip-select Control */
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u16 csar1;
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u16 res3;
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u32 csmr1;
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u16 res4;
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u16 cscr1;
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u16 csar2;
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u16 res5;
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u32 csmr2;
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u16 res6;
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u16 cscr2;
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u16 csar3;
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u16 res7;
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u32 csmr3;
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u16 res8;
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u16 cscr3;
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u16 csar4;
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u16 res9;
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u32 csmr4;
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u16 res10;
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u16 cscr4;
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u16 csar5;
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u16 res11;
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u32 csmr5;
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u16 res12;
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u16 cscr5;
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u16 csar6;
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u16 res13;
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u32 csmr6;
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u16 res14;
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u16 cscr6;
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u16 csar7;
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u16 res15;
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u32 csmr7;
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u16 res16;
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u16 cscr7;
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} fbcs_t;
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#else
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typedef struct fbcs {
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u32 csar0; /* Chip-select Address */
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u32 csmr0; /* Chip-select Mask */
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u32 cscr0; /* Chip-select Control */
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u32 csar1;
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u32 csmr1;
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u32 cscr1;
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u32 csar2;
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u32 csmr2;
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u32 cscr2;
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u32 csar3;
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u32 csmr3;
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u32 cscr3;
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u32 csar4;
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u32 csmr4;
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u32 cscr4;
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u32 csar5;
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u32 csmr5;
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u32 cscr5;
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u32 csar6;
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u32 csmr6;
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u32 cscr6;
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u32 csar7;
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u32 csmr7;
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u32 cscr7;
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} fbcs_t;
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#endif
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#define FBCS_CSAR_BA(x) ((x) & 0xFFFF0000)
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#define FBCS_CSMR_BAM(x) (((x) & 0xFFFF) << 16)
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#define FBCS_CSMR_BAM_MASK (0x0000FFFF)
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#define FBCS_CSMR_BAM_4G (0xFFFF0000)
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#define FBCS_CSMR_BAM_2G (0x7FFF0000)
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#define FBCS_CSMR_BAM_1G (0x3FFF0000)
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#define FBCS_CSMR_BAM_1024M (0x3FFF0000)
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#define FBCS_CSMR_BAM_512M (0x1FFF0000)
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#define FBCS_CSMR_BAM_256M (0x0FFF0000)
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#define FBCS_CSMR_BAM_128M (0x07FF0000)
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#define FBCS_CSMR_BAM_64M (0x03FF0000)
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#define FBCS_CSMR_BAM_32M (0x01FF0000)
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#define FBCS_CSMR_BAM_16M (0x00FF0000)
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#define FBCS_CSMR_BAM_8M (0x007F0000)
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#define FBCS_CSMR_BAM_4M (0x003F0000)
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#define FBCS_CSMR_BAM_2M (0x001F0000)
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#define FBCS_CSMR_BAM_1M (0x000F0000)
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#define FBCS_CSMR_BAM_1024K (0x000F0000)
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#define FBCS_CSMR_BAM_512K (0x00070000)
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#define FBCS_CSMR_BAM_256K (0x00030000)
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#define FBCS_CSMR_BAM_128K (0x00010000)
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#define FBCS_CSMR_BAM_64K (0x00000000)
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#ifdef CONFIG_M5249
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#define FBCS_CSMR_WP (0x00000080)
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#define FBCS_CSMR_AM (0x00000040)
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#define FBCS_CSMR_CI (0x00000020)
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#define FBCS_CSMR_SC (0x00000010)
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#define FBCS_CSMR_SD (0x00000008)
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#define FBCS_CSMR_UC (0x00000004)
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#define FBCS_CSMR_UD (0x00000002)
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#else
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#define FBCS_CSMR_WP (0x00000100)
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#endif
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#define FBCS_CSMR_V (0x00000001) /* Valid bit */
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#ifdef CONFIG_M5235
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#define FBCS_CSCR_SRWS(x) (((x) & 0x3) << 14)
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#define FBCS_CSCR_IWS(x) (((x) & 0xF) << 10)
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#define FBCS_CSCR_AA_ON (1 << 8)
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#define FBCS_CSCR_AA_OFF (0 << 8)
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#define FBCS_CSCR_PS_32 (0 << 6)
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#define FBCS_CSCR_PS_16 (2 << 6)
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#define FBCS_CSCR_PS_8 (1 << 6)
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#define FBCS_CSCR_BEM_ON (1 << 5)
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#define FBCS_CSCR_BEM_OFF (0 << 5)
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#define FBCS_CSCR_BSTR_ON (1 << 4)
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#define FBCS_CSCR_BSTR_OFF (0 << 4)
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#define FBCS_CSCR_BSTW_ON (1 << 3)
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#define FBCS_CSCR_BSTW_OFF (0 << 3)
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#define FBCS_CSCR_SWWS(x) (((x) & 0x7) << 0)
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#else
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#define FBCS_CSCR_SWS(x) (((x) & 0x3F) << 26)
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#define FBCS_CSCR_SWS_MASK (0x03FFFFFF)
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#define FBCS_CSCR_SWSEN (0x00800000)
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#define FBCS_CSCR_ASET(x) (((x) & 0x03) << 20)
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#define FBCS_CSCR_ASET_MASK (0xFFCFFFFF)
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#define FBCS_CSCR_RDAH(x) (((x) & 0x03) << 18)
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#define FBCS_CSCR_RDAH_MASK (0xFFF3FFFF)
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#define FBCS_CSCR_WRAH(x) (((x) & 0x03) << 16)
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#define FBCS_CSCR_WRAH_MASK (0xFFFCFFFF)
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#define FBCS_CSCR_WS(x) (((x) & 0x3F) << 10)
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#define FBCS_CSCR_WS_MASK (0xFFFF03FF)
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#define FBCS_CSCR_SBM (0x00000200)
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#define FBCS_CSCR_AA (0x00000100)
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#define FBCS_CSCR_PS(x) (((x) & 0x03) << 6)
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#define FBCS_CSCR_PS_MASK (0xFFFFFF3F)
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#define FBCS_CSCR_BEM (0x00000020)
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#define FBCS_CSCR_BSTR (0x00000010)
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#define FBCS_CSCR_BSTW (0x00000008)
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#define FBCS_CSCR_PS_16 (0x00000080)
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#define FBCS_CSCR_PS_8 (0x00000040)
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#define FBCS_CSCR_PS_32 (0x00000000)
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#endif
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#endif /* __FLEXBUS_H */
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