mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
161 lines
5.6 KiB
C
161 lines
5.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* EDMA Internal Memory Map
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*/
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#ifndef __EDMA_H__
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#define __EDMA_H__
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/*********************************************************************
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* Enhanced DMA (EDMA)
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*********************************************************************/
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/* eDMA module registers */
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typedef struct edma_ctrl {
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u32 cr; /* 0x00 Control Register */
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u32 es; /* 0x04 Error Status Register */
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u16 res1[3]; /* 0x08 - 0x0D */
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u16 erq; /* 0x0E Enable Request Register */
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u16 res2[3]; /* 0x10 - 0x15 */
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u16 eei; /* 0x16 Enable Error Interrupt Request */
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u8 serq; /* 0x18 Set Enable Request */
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u8 cerq; /* 0x19 Clear Enable Request */
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u8 seei; /* 0x1A Set En Error Interrupt Request */
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u8 ceei; /* 0x1B Clear En Error Interrupt Request */
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u8 cint; /* 0x1C Clear Interrupt Enable */
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u8 cerr; /* 0x1D Clear Error */
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u8 ssrt; /* 0x1E Set START Bit */
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u8 cdne; /* 0x1F Clear DONE Status Bit */
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u16 res3[3]; /* 0x20 - 0x25 */
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u16 intr; /* 0x26 Interrupt Request */
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u16 res4[3]; /* 0x28 - 0x2D */
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u16 err; /* 0x2E Error Register */
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u32 res5[52]; /* 0x30 - 0xFF */
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u8 dchpri0; /* 0x100 Channel 0 Priority */
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u8 dchpri1; /* 0x101 Channel 1 Priority */
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u8 dchpri2; /* 0x102 Channel 2 Priority */
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u8 dchpri3; /* 0x103 Channel 3 Priority */
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u8 dchpri4; /* 0x104 Channel 4 Priority */
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u8 dchpri5; /* 0x105 Channel 5 Priority */
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u8 dchpri6; /* 0x106 Channel 6 Priority */
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u8 dchpri7; /* 0x107 Channel 7 Priority */
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u8 dchpri8; /* 0x108 Channel 8 Priority */
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u8 dchpri9; /* 0x109 Channel 9 Priority */
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u8 dchpri10; /* 0x110 Channel 10 Priority */
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u8 dchpri11; /* 0x111 Channel 11 Priority */
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u8 dchpri12; /* 0x112 Channel 12 Priority */
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u8 dchpri13; /* 0x113 Channel 13 Priority */
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u8 dchpri14; /* 0x114 Channel 14 Priority */
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u8 dchpri15; /* 0x115 Channel 15 Priority */
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} edma_t;
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/* TCD - eDMA*/
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typedef struct tcd_ctrl {
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u32 saddr; /* 0x00 Source Address */
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u16 attr; /* 0x04 Transfer Attributes */
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u16 soff; /* 0x06 Signed Source Address Offset */
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u32 nbytes; /* 0x08 Minor Byte Count */
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u32 slast; /* 0x0C Last Source Address Adjustment */
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u32 daddr; /* 0x10 Destination address */
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u16 citer; /* 0x14 Cur Minor Loop Link, Major Loop Cnt */
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u16 doff; /* 0x16 Signed Destination Address Offset */
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u32 dlast_sga; /* 0x18 Last Dest Adr Adj/Scatter Gather Adr */
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u16 biter; /* 0x1C Minor Loop Lnk, Major Loop Cnt */
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u16 csr; /* 0x1E Control and Status */
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} tcd_st;
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typedef struct tcd_multiple {
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tcd_st tcd[16];
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} tcd_t;
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/* Bit definitions and macros for EPPAR */
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#define EPORT_EPPAR_EPPA1(x) (((x)&0x0003)<<2)
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#define EPORT_EPPAR_EPPA2(x) (((x)&0x0003)<<4)
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#define EPORT_EPPAR_EPPA3(x) (((x)&0x0003)<<6)
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#define EPORT_EPPAR_EPPA4(x) (((x)&0x0003)<<8)
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#define EPORT_EPPAR_EPPA5(x) (((x)&0x0003)<<10)
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#define EPORT_EPPAR_EPPA6(x) (((x)&0x0003)<<12)
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#define EPORT_EPPAR_EPPA7(x) (((x)&0x0003)<<14)
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#define EPORT_EPPAR_LEVEL (0)
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#define EPORT_EPPAR_RISING (1)
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#define EPORT_EPPAR_FALLING (2)
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#define EPORT_EPPAR_BOTH (3)
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#define EPORT_EPPAR_EPPA7_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA7_RISING (0x4000)
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#define EPORT_EPPAR_EPPA7_FALLING (0x8000)
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#define EPORT_EPPAR_EPPA7_BOTH (0xC000)
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#define EPORT_EPPAR_EPPA6_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA6_RISING (0x1000)
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#define EPORT_EPPAR_EPPA6_FALLING (0x2000)
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#define EPORT_EPPAR_EPPA6_BOTH (0x3000)
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#define EPORT_EPPAR_EPPA5_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA5_RISING (0x0400)
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#define EPORT_EPPAR_EPPA5_FALLING (0x0800)
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#define EPORT_EPPAR_EPPA5_BOTH (0x0C00)
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#define EPORT_EPPAR_EPPA4_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA4_RISING (0x0100)
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#define EPORT_EPPAR_EPPA4_FALLING (0x0200)
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#define EPORT_EPPAR_EPPA4_BOTH (0x0300)
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#define EPORT_EPPAR_EPPA3_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA3_RISING (0x0040)
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#define EPORT_EPPAR_EPPA3_FALLING (0x0080)
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#define EPORT_EPPAR_EPPA3_BOTH (0x00C0)
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#define EPORT_EPPAR_EPPA2_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA2_RISING (0x0010)
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#define EPORT_EPPAR_EPPA2_FALLING (0x0020)
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#define EPORT_EPPAR_EPPA2_BOTH (0x0030)
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#define EPORT_EPPAR_EPPA1_LEVEL (0x0000)
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#define EPORT_EPPAR_EPPA1_RISING (0x0004)
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#define EPORT_EPPAR_EPPA1_FALLING (0x0008)
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#define EPORT_EPPAR_EPPA1_BOTH (0x000C)
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/* Bit definitions and macros for EPDDR */
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#define EPORT_EPDDR_EPDD1 (0x02)
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#define EPORT_EPDDR_EPDD2 (0x04)
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#define EPORT_EPDDR_EPDD3 (0x08)
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#define EPORT_EPDDR_EPDD4 (0x10)
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#define EPORT_EPDDR_EPDD5 (0x20)
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#define EPORT_EPDDR_EPDD6 (0x40)
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#define EPORT_EPDDR_EPDD7 (0x80)
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/* Bit definitions and macros for EPIER */
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#define EPORT_EPIER_EPIE1 (0x02)
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#define EPORT_EPIER_EPIE2 (0x04)
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#define EPORT_EPIER_EPIE3 (0x08)
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#define EPORT_EPIER_EPIE4 (0x10)
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#define EPORT_EPIER_EPIE5 (0x20)
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#define EPORT_EPIER_EPIE6 (0x40)
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#define EPORT_EPIER_EPIE7 (0x80)
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/* Bit definitions and macros for EPDR */
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#define EPORT_EPDR_EPD1 (0x02)
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#define EPORT_EPDR_EPD2 (0x04)
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#define EPORT_EPDR_EPD3 (0x08)
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#define EPORT_EPDR_EPD4 (0x10)
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#define EPORT_EPDR_EPD5 (0x20)
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#define EPORT_EPDR_EPD6 (0x40)
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#define EPORT_EPDR_EPD7 (0x80)
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/* Bit definitions and macros for EPPDR */
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#define EPORT_EPPDR_EPPD1 (0x02)
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#define EPORT_EPPDR_EPPD2 (0x04)
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#define EPORT_EPPDR_EPPD3 (0x08)
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#define EPORT_EPPDR_EPPD4 (0x10)
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#define EPORT_EPPDR_EPPD5 (0x20)
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#define EPORT_EPPDR_EPPD6 (0x40)
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#define EPORT_EPPDR_EPPD7 (0x80)
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/* Bit definitions and macros for EPFR */
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#define EPORT_EPFR_EPF1 (0x02)
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#define EPORT_EPFR_EPF2 (0x04)
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#define EPORT_EPFR_EPF3 (0x08)
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#define EPORT_EPFR_EPF4 (0x10)
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#define EPORT_EPFR_EPF5 (0x20)
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#define EPORT_EPFR_EPF6 (0x40)
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#define EPORT_EPFR_EPF7 (0x80)
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#endif /* __EDMA_H__ */
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