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https://github.com/brain-hackers/u-boot-brain
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f7cf291aa7
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
39 lines
992 B
C
39 lines
992 B
C
/*
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* Special Function Register (SFR)
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*
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* Copyright (C) 2014 Atmel
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* Bo Shen <voice.shen@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __SAMA5_SFR_H
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#define __SAMA5_SFR_H
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struct atmel_sfr {
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u32 reserved1; /* 0x00 */
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u32 ddrcfg; /* 0x04: DDR Configuration Register */
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u32 reserved2; /* 0x08 */
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u32 reserved3; /* 0x0c */
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u32 ohciicr; /* 0x10: OHCI Interrupt Configuration Register */
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u32 ohciisr; /* 0x14: OHCI Interrupt Status Register */
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u32 reserved4[4]; /* 0x18 ~ 0x24 */
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u32 secure; /* 0x28: Security Configuration Register */
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u32 reserved5[5]; /* 0x2c ~ 0x3c */
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u32 ebicfg; /* 0x40: EBI Configuration Register */
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u32 reserved6[2]; /* 0x44 ~ 0x48 */
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u32 sn0; /* 0x4c */
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u32 sn1; /* 0x50 */
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u32 aicredir; /* 0x54 */
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u32 l2cc_hramc; /* 0x58 */
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};
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/* Bit field in DDRCFG */
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#define ATMEL_SFR_DDRCFG_FDQIEN 0x00010000
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#define ATMEL_SFR_DDRCFG_FDQSIEN 0x00020000
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/* Bit field in AICREDIR */
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#define ATMEL_SFR_AICREDIR_NSAIC 0x00000001
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#endif
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