Jagan Teki 337fcdc06b clk: sunxi: Add Allwinner H6 CLK driver ... Add initial clock driver for Allwinner H6. - Implement UART bus clocks via ccu_clk_gate table for H6, so it can accessed in common clk enable and disable functions from clk_sunxi.c - Implement UART bus resets via ccu_reset table for H6, so it can accessed in common reset deassert and assert functions from reset-sunxi.c Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>		2019-01-18 22:19:09 +05:30
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clk_a10.c	clk: sunxi: Implement UART clocks	2019-01-18 22:19:09 +05:30
clk_a10s.c	clk: sunxi: Implement UART clocks	2019-01-18 22:19:09 +05:30
clk_a23.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_a31.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_a64.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_a83t.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_h3.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_h6.c	clk: sunxi: Add Allwinner H6 CLK driver	2019-01-18 22:19:09 +05:30
clk_r40.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
clk_sunxi.c	clk: Add Allwinner A64 CLK driver	2019-01-18 22:19:08 +05:30
clk_v3s.c	clk: sunxi: Implement UART resets	2019-01-18 22:19:09 +05:30
Kconfig	clk: sunxi: Add Allwinner H6 CLK driver	2019-01-18 22:19:09 +05:30
Makefile	clk: sunxi: Add Allwinner H6 CLK driver	2019-01-18 22:19:09 +05:30