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062ef1a662
T1040RDB is Freescale Reference Design Board supporting
the T1040 QorIQ Power Architecture™ processor.
T1040RDB board Overview
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- Four e5500 cores, each with a private 256 KB L2 cache
- 256 KB shared L3 CoreNet platform cache (CPC)
- Interconnect CoreNet platform
- 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and interleaving
support
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
for the following functions:
- Packet parsing, classification, and distribution
- Queue management for scheduling, packet sequencing, and congestion
management
- Cryptography Acceleration
- RegEx Pattern Matching Acceleration
- IEEE Std 1588 support
- Hardware buffer management for buffer allocation and deallocation
- Ethernet interfaces
- Integrated 8-port Gigabit Ethernet switch
- Four 1 Gbps Ethernet controllers
- SERDES Connections, 8 lanes supporting:
- PCI
- SGMII
- QSGMII
- SATA 2.0
- DDR Controller 32-/64-bit DDR3L/DDR4 SDRAM memory controller with ECC and
Interleaving
-IFC/Local Bus
- NAND flash: 1GB 8-bit NAND flash
- NOR: 128MB 16-bit NOR Flash
- Ethernet
- Two on-board RGMII 10/100/1G ethernet ports.
- PHY #0 remains powered up during deep-sleep
- CPLD
- Clocks
- System and DDR clock (SYSCLK, “DDRCLK”)
- SERDES clocks
- Power Supplies
- USB
- Supports two USB 2.0 ports with integrated PHYs
- Two type A ports with 5V@1.5A per port.
- SDHC
- SDHC/SDXC connector
- SPI
- On-board 64MB SPI flash
- I2C
- Devices connected: EEPROM, thermal monitor, VID controller
- Other IO
- Two Serial ports
- ProfiBus port
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
[York Sun: fixed Makefile]
Acked-by: York Sun <yorksun@freescale.com>
77 lines
1.8 KiB
C
77 lines
1.8 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __DDR_H__
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#define __DDR_H__
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 2,
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.rank_density = 2147483648u,
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.capacity = 4294967296u,
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.primary_sdram_width = 64,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 1,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 2, /* ECC */
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1071,
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.caslat_x = 0x2fe << 4, /* 5,6,7,8,9,10,11,13 */
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.taa_ps = 13910,
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.twr_ps = 15000,
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.trcd_ps = 13910,
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.trrd_ps = 6000,
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.trp_ps = 13910,
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.tras_ps = 34000,
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.trc_ps = 48910,
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.trfc_ps = 260000,
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.twtr_ps = 7500,
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.trtp_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 35000,
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};
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struct board_specific_parameters {
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u32 n_ranks;
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u32 datarate_mhz_high;
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u32 rank_gb;
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u32 clk_adjust;
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u32 wrlvl_start;
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u32 wrlvl_ctl_2;
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u32 wrlvl_ctl_3;
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u32 cpo;
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u32 write_data_delay;
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u32 force_2t;
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};
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/*
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* These tables contain all valid speeds we want to override with board
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* specific parameters. datarate_mhz_high values need to be in ascending order
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* for each n_ranks group.
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*/
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static const struct board_specific_parameters udimm0[] = {
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/*
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* memory controller 0
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* num| hi| rank| clk| wrlvl | wrlvl | wrlvl | cpo |wrdata|2T
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* ranks| mhz| GB |adjst| start | ctl2 | ctl3 | |delay |
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*/
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{2, 1066, 4, 8, 4, 0x05070609, 0x08090a08, 0xff, 2, 0},
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{2, 1350, 4, 4, 8, 0x0809090b, 0x0c0c0d0a, 0xff, 2, 0},
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{2, 1350, 0, 5, 7, 0x0709090b, 0x0c0c0d09, 0xff, 2, 0},
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{2, 1666, 4, 4, 8, 0x080a0a0d, 0x0d10100b, 0xff, 2, 0},
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{2, 1666, 0, 5, 7, 0x080a0a0c, 0x0d0d0e0a, 0xff, 2, 0},
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{}
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};
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static const struct board_specific_parameters *udimms[] = {
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udimm0,
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};
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#endif
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