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https://github.com/brain-hackers/u-boot-brain
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515e8174f5
With Apollo Lake we need to support a normal cache, which almost never changes and a much smaller 'variable' cache which changes every time. Update the code to add a cache type, use an array for the caches and use a for loop to iterate over the caches. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
39 lines
1012 B
C
39 lines
1012 B
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2014, Bin Meng <bmeng.cn@gmail.com>
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*/
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#include <common.h>
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#include <asm/fsp/fsp_support.h>
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int dram_init(void)
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{
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int ret;
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/* The FSP has already set up DRAM, so grab the info we need */
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ret = fsp_scan_for_ram_size();
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if (ret)
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return ret;
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if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
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struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
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mrc->buf = fsp_get_nvs_data(gd->arch.hob_list, &mrc->len);
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}
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return 0;
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}
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary.
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* It overrides the default implementation found elsewhere which simply
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* picks the end of ram, wherever that may be. The location of the stack,
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* the relocation address, and how far U-Boot is moved by relocation are
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* set in the global data structure.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return fsp_get_usable_lowmem_top(gd->arch.hob_list);
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}
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