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https://github.com/brain-hackers/u-boot-brain
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b84d4d0932
This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
45 lines
955 B
C
45 lines
955 B
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Special driver to handle of-platdata
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*
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* Copyright 2019 Google LLC
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*
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* Some code from coreboot lpss.c
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*/
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#include <common.h>
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#include <dm.h>
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#include <pci.h>
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#include <asm/io.h>
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#include <asm/lpss.h>
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enum {
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LPSS_RESET_CTL_REG = 0x204,
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/*
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* Bit 1:0 controls LPSS controller reset.
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*
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* 00 ->LPSS Host Controller is in reset (Reset Asserted)
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* 01/10 ->Reserved
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* 11 ->LPSS Host Controller is NOT at reset (Reset Released)
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*/
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LPSS_CNT_RST_RELEASE = 3,
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/* Power management control and status register */
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PME_CTRL_STATUS = 0x84,
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/* Bit 1:0 Powerstate, controls D0 and D3 state */
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POWER_STATE_MASK = 3,
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};
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/* Take controller out of reset */
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void lpss_reset_release(void *regs)
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{
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writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG);
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}
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void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state)
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{
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dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state);
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}
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