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https://github.com/brain-hackers/u-boot-brain
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33672c970b
On Altera SoCFPGA, upon either cold-boot or power-on reset, the Denali NAND IP is initialized by the BootROM ; upon warm-reset, the Denali NAND IP is NOT initialized by BootROM. In fact, upon warm-reset, the SoCFPGA BootROM checks whether the SPL image in on-chip RAM is valid and if so, completely skips re-loading the SPL from the boot media. This does sometimes lead to problems where the software left the boot media in inconsistent state before warm-reset, and because the BootROM does not reset the boot media, the boot media is left in this inconsistent state, often until another component attempts to access the boot media and fails with an difficult to debug failure. To mitigate this problem, the SPL on Altera SoCFPGA always resets all the IPs on the SoC early on boot. This results in a couple of register values, pre-programmed by the BootROM, to be lost during this reset. To restore correct operation of the IP on SoCFPGA, these values must be programmed back into the controller by the driver. Note that on other SoCs which do not use the HW-controlled bootstrap, more registers may have to be programmed. This also aligns the SPL behavior with the full Denali NAND driver, which sets these values in denali_hw_init(). Signed-off-by: Marek Vasut <marex@denx.de> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> |
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| .. | ||
| nand | ||
| onenand | ||
| spi | ||
| ubi | ||
| ubispl | ||
| altera_qspi.c | ||
| cfi_flash.c | ||
| cfi_mtd.c | ||
| hbmc-am654.c | ||
| jedec_flash.c | ||
| Kconfig | ||
| Makefile | ||
| mtd_uboot.c | ||
| mtd-uclass.c | ||
| mtdconcat.c | ||
| mtdcore.c | ||
| mtdcore.h | ||
| mtdpart.c | ||
| mw_eeprom.c | ||
| pic32_flash.c | ||
| renesas_rpc_hf.c | ||
| st_smi.c | ||
| stm32_flash.c | ||
| stm32_flash.h | ||