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![Andre Przywara](/assets/img/avatar_default.png)
The DRAM controller in the Allwinner H5 SoC is again very similar to the one in the H3 and A64. Based on the existing socid parameter, add support for this controller by reusing the bulk of the code and only deviating where needed. These new bits set or cleared here and there have been mostly found by looking at DRAM register dumps after using the H5 boot0 and comparing them to what we set in the code. So for now it's mostly unclear what those bits actually mean - hence the missing names and comments. Also add the delay line parameters taken from the boot0 and libdram disassembly. Register setup differences between H5 and H3 are courtesy of Jens Kuske. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
735 lines
23 KiB
C
735 lines
23 KiB
C
/*
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* sun8i H3 platform dram controller init
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*
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* (C) Copyright 2007-2015 Allwinner Technology Co.
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* Jerry Wang <wangflord@allwinnertech.com>
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* (C) Copyright 2015 Vishnu Patekar <vishnupatekar0510@gmail.com>
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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* (C) Copyright 2015 Jens Kuske <jenskuske@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/dram.h>
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#include <asm/arch/cpu.h>
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#include <linux/kconfig.h>
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/*
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* The delay parameters below allow to allegedly specify delay times of some
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* unknown unit for each individual bit trace in each of the four data bytes
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* the 32-bit wide access consists of. Also three control signals can be
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* adjusted individually.
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*/
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#define BITS_PER_BYTE 8
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#define NR_OF_BYTE_LANES (32 / BITS_PER_BYTE)
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/* The eight data lines (DQn) plus DM, DQS and DQSN */
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#define LINES_PER_BYTE_LANE (BITS_PER_BYTE + 3)
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struct dram_para {
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u16 page_size;
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u8 bus_width;
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u8 dual_rank;
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u8 row_bits;
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const u8 dx_read_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 dx_write_delays[NR_OF_BYTE_LANES][LINES_PER_BYTE_LANE];
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const u8 ac_delays[31];
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};
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static inline int ns_to_t(int nanoseconds)
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{
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const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
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return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
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}
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static void mctl_phy_init(u32 val)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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writel(val | PIR_INIT, &mctl_ctl->pir);
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mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
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}
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static void mctl_set_bit_delays(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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int i, j;
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clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
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for (i = 0; i < NR_OF_BYTE_LANES; i++)
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for (j = 0; j < LINES_PER_BYTE_LANE; j++)
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writel(DXBDLR_WRITE_DELAY(para->dx_write_delays[i][j]) |
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DXBDLR_READ_DELAY(para->dx_read_delays[i][j]),
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&mctl_ctl->dx[i].bdlr[j]);
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for (i = 0; i < 31; i++)
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writel(ACBDLR_WRITE_DELAY(para->ac_delays[i]),
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&mctl_ctl->acbdlr[i]);
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setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
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}
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enum {
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MBUS_PORT_CPU = 0,
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MBUS_PORT_GPU = 1,
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MBUS_PORT_UNUSED = 2,
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MBUS_PORT_DMA = 3,
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MBUS_PORT_VE = 4,
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MBUS_PORT_CSI = 5,
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MBUS_PORT_NAND = 6,
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MBUS_PORT_SS = 7,
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MBUS_PORT_TS = 8,
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MBUS_PORT_DI = 9,
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MBUS_PORT_DE = 10,
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MBUS_PORT_DE_CFD = 11,
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};
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enum {
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MBUS_QOS_LOWEST = 0,
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MBUS_QOS_LOW,
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MBUS_QOS_HIGH,
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MBUS_QOS_HIGHEST
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};
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inline void mbus_configure_port(u8 port,
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bool bwlimit,
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bool priority,
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u8 qos, /* MBUS_QOS_LOWEST .. MBUS_QOS_HIGEST */
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u8 waittime, /* 0 .. 0xf */
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u8 acs, /* 0 .. 0xff */
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u16 bwl0, /* 0 .. 0xffff, bandwidth limit in MB/s */
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u16 bwl1,
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u16 bwl2)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
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| (priority ? (1 << 1) : 0)
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| ((qos & 0x3) << 2)
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| ((waittime & 0xf) << 4)
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| ((acs & 0xff) << 8)
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| (bwl0 << 16) );
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const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
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debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
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writel(cfg0, &mctl_com->mcr[port][0]);
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writel(cfg1, &mctl_com->mcr[port][1]);
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}
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#define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
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mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
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MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
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static void mctl_set_master_priority_h3(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel((1 << 16) | (400 << 0), &mctl_com->bwcr);
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/* set cpu high priority */
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writel(0x00000001, &mctl_com->mapr);
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MBUS_CONF( CPU, true, HIGHEST, 0, 512, 256, 128);
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MBUS_CONF( GPU, true, HIGH, 0, 1536, 1024, 256);
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MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
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MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
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MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
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MBUS_CONF( CSI, true, HIGHEST, 0, 256, 128, 32);
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MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
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MBUS_CONF( DE, true, HIGHEST, 3, 8192, 6120, 1024);
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MBUS_CONF(DE_CFD, true, HIGH, 0, 1024, 288, 64);
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}
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static void mctl_set_master_priority_a64(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel(399, &mctl_com->tmr);
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writel((1 << 16), &mctl_com->bwcr);
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/* Port 2 is reserved per Allwinner's linux-3.10 source, yet they
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* initialise it */
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MBUS_CONF( CPU, true, HIGHEST, 0, 160, 100, 80);
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MBUS_CONF( GPU, false, HIGH, 0, 1536, 1400, 256);
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MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
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MBUS_CONF( DMA, true, HIGH, 0, 256, 80, 100);
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MBUS_CONF( VE, true, HIGH, 0, 1792, 1600, 256);
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MBUS_CONF( CSI, true, HIGH, 0, 256, 128, 0);
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MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
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MBUS_CONF( DE, true, HIGH, 2, 8192, 6144, 2048);
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MBUS_CONF(DE_CFD, true, HIGH, 0, 1280, 144, 64);
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writel(0x81000004, &mctl_com->mdfs_bwlr[2]);
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}
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static void mctl_set_master_priority_h5(void)
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{
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struct sunxi_mctl_com_reg * const mctl_com =
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(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
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/* enable bandwidth limit windows and set windows size 1us */
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writel(399, &mctl_com->tmr);
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writel((1 << 16), &mctl_com->bwcr);
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/* set cpu high priority */
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writel(0x00000001, &mctl_com->mapr);
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/* Port 2 is reserved per Allwinner's linux-3.10 source, yet
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* they initialise it */
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MBUS_CONF( CPU, true, HIGHEST, 0, 300, 260, 150);
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MBUS_CONF( GPU, true, HIGHEST, 0, 600, 400, 200);
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MBUS_CONF(UNUSED, true, HIGHEST, 0, 512, 256, 96);
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MBUS_CONF( DMA, true, HIGHEST, 0, 256, 128, 32);
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MBUS_CONF( VE, true, HIGHEST, 0, 1900, 1500, 1000);
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MBUS_CONF( CSI, true, HIGHEST, 0, 150, 120, 100);
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MBUS_CONF( NAND, true, HIGH, 0, 256, 128, 64);
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MBUS_CONF( SS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( TS, true, HIGHEST, 0, 256, 128, 64);
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MBUS_CONF( DI, true, HIGH, 0, 1024, 256, 64);
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MBUS_CONF( DE, true, HIGHEST, 3, 3400, 2400, 1024);
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MBUS_CONF(DE_CFD, true, HIGHEST, 0, 600, 400, 200);
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}
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static void mctl_set_master_priority(uint16_t socid)
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{
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switch (socid) {
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case SOCID_H3:
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mctl_set_master_priority_h3();
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return;
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case SOCID_A64:
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mctl_set_master_priority_a64();
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return;
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case SOCID_H5:
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mctl_set_master_priority_h5();
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return;
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}
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}
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static void mctl_set_timing_params(uint16_t socid, struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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u8 tccd = 2;
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u8 tfaw = ns_to_t(50);
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u8 trrd = max(ns_to_t(10), 4);
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u8 trcd = ns_to_t(15);
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u8 trc = ns_to_t(53);
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u8 txp = max(ns_to_t(8), 3);
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u8 twtr = max(ns_to_t(8), 4);
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u8 trtp = max(ns_to_t(8), 4);
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u8 twr = max(ns_to_t(15), 3);
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u8 trp = ns_to_t(15);
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u8 tras = ns_to_t(38);
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u16 trefi = ns_to_t(7800) / 32;
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u16 trfc = ns_to_t(350);
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u8 tmrw = 0;
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u8 tmrd = 4;
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u8 tmod = 12;
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u8 tcke = 3;
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u8 tcksrx = 5;
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u8 tcksre = 5;
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u8 tckesr = 4;
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u8 trasmax = 24;
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u8 tcl = 6; /* CL 12 */
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u8 tcwl = 4; /* CWL 8 */
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u8 t_rdata_en = 4;
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u8 wr_latency = 2;
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u32 tdinit0 = (500 * CONFIG_DRAM_CLK) + 1; /* 500us */
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u32 tdinit1 = (360 * CONFIG_DRAM_CLK) / 1000 + 1; /* 360ns */
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u32 tdinit2 = (200 * CONFIG_DRAM_CLK) + 1; /* 200us */
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u32 tdinit3 = (1 * CONFIG_DRAM_CLK) + 1; /* 1us */
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u8 twtp = tcwl + 2 + twr; /* WL + BL / 2 + tWR */
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u8 twr2rd = tcwl + 2 + twtr; /* WL + BL / 2 + tWTR */
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u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */
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/* set mode register */
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writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */
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writel(0x40, &mctl_ctl->mr[1]);
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writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */
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writel(0x0, &mctl_ctl->mr[3]);
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/* set DRAM timing */
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writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
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DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
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&mctl_ctl->dramtmg[0]);
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writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
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&mctl_ctl->dramtmg[1]);
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writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
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DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
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&mctl_ctl->dramtmg[2]);
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writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
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&mctl_ctl->dramtmg[3]);
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writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
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DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
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writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
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DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
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&mctl_ctl->dramtmg[5]);
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/* set two rank timing */
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clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
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((socid == SOCID_H5 ? 0x33 : 0x66) << 8) | (0x10 << 0));
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/* set PHY interface timing, write latency and read latency configure */
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writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
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(wr_latency << 0), &mctl_ctl->pitmg[0]);
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/* set PHY timing, PTR0-2 use default */
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writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
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writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
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/* set refresh timing */
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writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
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}
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static u32 bin_to_mgray(int val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
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0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
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0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
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};
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return lookup_table[clamp(val, 0, 31)];
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}
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static int mgray_to_bin(u32 val)
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{
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static const u8 lookup_table[32] = {
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0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
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0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
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0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
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0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
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};
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return lookup_table[val & 0x1f];
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}
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static void mctl_h3_zq_calibration_quirk(struct dram_para *para)
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{
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struct sunxi_mctl_ctl_reg * const mctl_ctl =
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(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
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if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
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(readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
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u32 reg_val;
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clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
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CONFIG_DRAM_ZQ & 0xffff);
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writel(PIR_CLRSR, &mctl_ctl->pir);
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mctl_phy_init(PIR_ZCAL);
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reg_val = readl(&mctl_ctl->zqdr[0]);
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reg_val &= (0x1f << 16) | (0x1f << 0);
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reg_val |= reg_val << 8;
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writel(reg_val, &mctl_ctl->zqdr[0]);
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reg_val = readl(&mctl_ctl->zqdr[1]);
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reg_val &= (0x1f << 16) | (0x1f << 0);
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reg_val |= reg_val << 8;
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writel(reg_val, &mctl_ctl->zqdr[1]);
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writel(reg_val, &mctl_ctl->zqdr[2]);
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} else {
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int i;
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u16 zq_val[6];
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u8 val;
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writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
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for (i = 0; i < 6; i++) {
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u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
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writel((zq << 20) | (zq << 16) | (zq << 12) |
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(zq << 8) | (zq << 4) | (zq << 0),
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&mctl_ctl->zqcr);
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writel(PIR_CLRSR, &mctl_ctl->pir);
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mctl_phy_init(PIR_ZCAL);
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zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
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writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
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writel(PIR_CLRSR, &mctl_ctl->pir);
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mctl_phy_init(PIR_ZCAL);
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val = readl(&mctl_ctl->zqdr[0]) >> 24;
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zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
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}
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writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
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writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
|
|
writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
|
|
}
|
|
}
|
|
|
|
static void mctl_set_cr(struct dram_para *para)
|
|
{
|
|
struct sunxi_mctl_com_reg * const mctl_com =
|
|
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
|
|
|
|
writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
|
|
MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
|
|
(para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
|
|
MCTL_CR_PAGE_SIZE(para->page_size) |
|
|
MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
|
|
}
|
|
|
|
static void mctl_sys_init(uint16_t socid, struct dram_para *para)
|
|
{
|
|
struct sunxi_ccm_reg * const ccm =
|
|
(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
|
|
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
|
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
|
|
|
clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
|
|
clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
|
|
clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
|
|
clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
|
|
clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
|
|
if (socid == SOCID_A64)
|
|
clrbits_le32(&ccm->pll11_cfg, CCM_PLL11_CTRL_EN);
|
|
udelay(10);
|
|
|
|
clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
|
|
udelay(1000);
|
|
|
|
if (socid == SOCID_A64) {
|
|
clock_set_pll11(CONFIG_DRAM_CLK * 2 * 1000000, false);
|
|
clrsetbits_le32(&ccm->dram_clk_cfg,
|
|
CCM_DRAMCLK_CFG_DIV_MASK |
|
|
CCM_DRAMCLK_CFG_SRC_MASK,
|
|
CCM_DRAMCLK_CFG_DIV(1) |
|
|
CCM_DRAMCLK_CFG_SRC_PLL11 |
|
|
CCM_DRAMCLK_CFG_UPD);
|
|
} else if (socid == SOCID_H3 || socid == SOCID_H5) {
|
|
clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
|
|
clrsetbits_le32(&ccm->dram_clk_cfg,
|
|
CCM_DRAMCLK_CFG_DIV_MASK |
|
|
CCM_DRAMCLK_CFG_SRC_MASK,
|
|
CCM_DRAMCLK_CFG_DIV(1) |
|
|
CCM_DRAMCLK_CFG_SRC_PLL5 |
|
|
CCM_DRAMCLK_CFG_UPD);
|
|
}
|
|
mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
|
|
|
|
setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
|
|
setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
|
|
setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
|
|
setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
|
|
|
|
setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
|
|
udelay(10);
|
|
|
|
writel(socid == SOCID_H5 ? 0x8000 : 0xc00e, &mctl_ctl->clken);
|
|
udelay(500);
|
|
}
|
|
|
|
/* These are more guessed based on some Allwinner code. */
|
|
#define DX_GCR_ODT_DYNAMIC (0x0 << 4)
|
|
#define DX_GCR_ODT_ALWAYS_ON (0x1 << 4)
|
|
#define DX_GCR_ODT_OFF (0x2 << 4)
|
|
|
|
static int mctl_channel_init(uint16_t socid, struct dram_para *para)
|
|
{
|
|
struct sunxi_mctl_com_reg * const mctl_com =
|
|
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
|
|
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
|
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
|
|
|
unsigned int i;
|
|
|
|
mctl_set_cr(para);
|
|
mctl_set_timing_params(socid, para);
|
|
mctl_set_master_priority(socid);
|
|
|
|
/* setting VTC, default disable all VT */
|
|
clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
|
|
if (socid == SOCID_H5)
|
|
setbits_le32(&mctl_ctl->pgcr[1], (1 << 24) | (1 << 26));
|
|
else
|
|
clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
|
|
|
|
/* increase DFI_PHY_UPD clock */
|
|
writel(PROTECT_MAGIC, &mctl_com->protect);
|
|
udelay(100);
|
|
clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
|
|
writel(0x0, &mctl_com->protect);
|
|
udelay(100);
|
|
|
|
/* set dramc odt */
|
|
for (i = 0; i < 4; i++) {
|
|
u32 clearmask = (0x3 << 4) | (0x1 << 1) | (0x3 << 2) |
|
|
(0x3 << 12) | (0x3 << 14);
|
|
u32 setmask = IS_ENABLED(CONFIG_DRAM_ODT_EN) ?
|
|
DX_GCR_ODT_DYNAMIC : DX_GCR_ODT_OFF;
|
|
|
|
if (socid == SOCID_H5) {
|
|
clearmask |= 0x2 << 8;
|
|
setmask |= 0x4 << 8;
|
|
}
|
|
clrsetbits_le32(&mctl_ctl->dx[i].gcr, clearmask, setmask);
|
|
}
|
|
|
|
/* AC PDR should always ON */
|
|
clrsetbits_le32(&mctl_ctl->aciocr, socid == SOCID_H5 ? (0x1 << 11) : 0,
|
|
0x1 << 1);
|
|
|
|
/* set DQS auto gating PD mode */
|
|
setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
|
|
|
|
if (socid == SOCID_H3) {
|
|
/* dx ddr_clk & hdr_clk dynamic mode */
|
|
clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
|
|
|
|
/* dphy & aphy phase select 270 degree */
|
|
clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
|
|
(0x1 << 10) | (0x2 << 8));
|
|
} else if (socid == SOCID_A64 || socid == SOCID_H5) {
|
|
/* dphy & aphy phase select ? */
|
|
clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
|
|
(0x0 << 10) | (0x3 << 8));
|
|
}
|
|
|
|
/* set half DQ */
|
|
if (para->bus_width != 32) {
|
|
writel(0x0, &mctl_ctl->dx[2].gcr);
|
|
writel(0x0, &mctl_ctl->dx[3].gcr);
|
|
}
|
|
|
|
/* data training configuration */
|
|
clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
|
|
(para->dual_rank ? 0x3 : 0x1) << 24);
|
|
|
|
mctl_set_bit_delays(para);
|
|
udelay(50);
|
|
|
|
if (socid == SOCID_H3) {
|
|
mctl_h3_zq_calibration_quirk(para);
|
|
|
|
mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
|
|
PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
|
|
} else if (socid == SOCID_A64 || socid == SOCID_H5) {
|
|
clrsetbits_le32(&mctl_ctl->zqcr, 0xffffff, CONFIG_DRAM_ZQ);
|
|
|
|
mctl_phy_init(PIR_ZCAL | PIR_PLLINIT | PIR_DCAL | PIR_PHYRST |
|
|
PIR_DRAMRST | PIR_DRAMINIT | PIR_QSGATE);
|
|
/* no PIR_QSGATE for H5 ???? */
|
|
}
|
|
|
|
/* detect ranks and bus width */
|
|
if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
|
|
/* only one rank */
|
|
if (((readl(&mctl_ctl->dx[0].gsr[0]) >> 24) & 0x2) ||
|
|
((readl(&mctl_ctl->dx[1].gsr[0]) >> 24) & 0x2)) {
|
|
clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
|
|
para->dual_rank = 0;
|
|
}
|
|
|
|
/* only half DQ width */
|
|
if (((readl(&mctl_ctl->dx[2].gsr[0]) >> 24) & 0x1) ||
|
|
((readl(&mctl_ctl->dx[3].gsr[0]) >> 24) & 0x1)) {
|
|
writel(0x0, &mctl_ctl->dx[2].gcr);
|
|
writel(0x0, &mctl_ctl->dx[3].gcr);
|
|
para->bus_width = 16;
|
|
}
|
|
|
|
mctl_set_cr(para);
|
|
udelay(20);
|
|
|
|
/* re-train */
|
|
mctl_phy_init(PIR_QSGATE);
|
|
if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
|
|
return 1;
|
|
}
|
|
|
|
/* check the dramc status */
|
|
mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
|
|
|
|
/* liuke added for refresh debug */
|
|
setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
|
|
udelay(10);
|
|
clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
|
|
udelay(10);
|
|
|
|
/* set PGCR3, CKE polarity */
|
|
if (socid == SOCID_H3)
|
|
writel(0x00aa0060, &mctl_ctl->pgcr[3]);
|
|
else if (socid == SOCID_A64 || socid == SOCID_H5)
|
|
writel(0xc0aa0060, &mctl_ctl->pgcr[3]);
|
|
|
|
/* power down zq calibration module for power save */
|
|
setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
|
|
|
|
/* enable master access */
|
|
writel(0xffffffff, &mctl_com->maer);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void mctl_auto_detect_dram_size(struct dram_para *para)
|
|
{
|
|
/* detect row address bits */
|
|
para->page_size = 512;
|
|
para->row_bits = 16;
|
|
mctl_set_cr(para);
|
|
|
|
for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
|
|
if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
|
|
break;
|
|
|
|
/* detect page size */
|
|
para->page_size = 8192;
|
|
mctl_set_cr(para);
|
|
|
|
for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
|
|
if (mctl_mem_matches(para->page_size))
|
|
break;
|
|
}
|
|
|
|
/*
|
|
* The actual values used here are taken from Allwinner provided boot0
|
|
* binaries, though they are probably board specific, so would likely benefit
|
|
* from invidual tuning for each board. Apparently a lot of boards copy from
|
|
* some Allwinner reference design, so we go with those generic values for now
|
|
* in the hope that they are reasonable for most (all?) boards.
|
|
*/
|
|
#define SUN8I_H3_DX_READ_DELAYS \
|
|
{{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
|
|
{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }, \
|
|
{ 18, 18, 18, 18, 18, 18, 18, 18, 18, 0, 0 }, \
|
|
{ 14, 14, 14, 14, 14, 14, 14, 14, 14, 0, 0 }}
|
|
#define SUN8I_H3_DX_WRITE_DELAYS \
|
|
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 10, 10 }, \
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 6, 6 }}
|
|
#define SUN8I_H3_AC_DELAYS \
|
|
{ 0, 0, 0, 0, 0, 0, 0, 0, \
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
|
0, 0, 0, 0, 0, 0, 0, 0, \
|
|
0, 0, 0, 0, 0, 0, 0 }
|
|
|
|
#define SUN50I_A64_DX_READ_DELAYS \
|
|
{{ 16, 16, 16, 16, 17, 16, 16, 17, 16, 1, 0 }, \
|
|
{ 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }, \
|
|
{ 16, 17, 17, 16, 16, 16, 16, 16, 16, 0, 0 }, \
|
|
{ 17, 17, 17, 17, 17, 17, 17, 17, 17, 1, 0 }}
|
|
#define SUN50I_A64_DX_WRITE_DELAYS \
|
|
{{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 15, 15 }, \
|
|
{ 0, 0, 0, 0, 1, 1, 1, 1, 0, 10, 10 }, \
|
|
{ 1, 0, 1, 1, 1, 1, 1, 1, 0, 11, 11 }, \
|
|
{ 1, 0, 0, 1, 1, 1, 1, 1, 0, 12, 12 }}
|
|
#define SUN50I_A64_AC_DELAYS \
|
|
{ 5, 5, 13, 10, 2, 5, 3, 3, \
|
|
0, 3, 3, 3, 1, 0, 0, 0, \
|
|
3, 4, 0, 3, 4, 1, 4, 0, \
|
|
1, 1, 0, 1, 13, 5, 4 }
|
|
|
|
#define SUN8I_H5_DX_READ_DELAYS \
|
|
{{ 14, 15, 17, 17, 17, 17, 17, 18, 17, 3, 3 }, \
|
|
{ 21, 21, 12, 22, 21, 21, 21, 21, 21, 3, 3 }, \
|
|
{ 16, 19, 19, 17, 22, 22, 21, 22, 19, 3, 3 }, \
|
|
{ 21, 21, 22, 22, 20, 21, 19, 19, 19, 3, 3 } }
|
|
#define SUN8I_H5_DX_WRITE_DELAYS \
|
|
{{ 1, 2, 3, 4, 3, 4, 4, 4, 6, 6, 6 }, \
|
|
{ 6, 6, 6, 5, 5, 5, 5, 5, 6, 6, 6 }, \
|
|
{ 0, 2, 4, 2, 6, 5, 5, 5, 6, 6, 6 }, \
|
|
{ 3, 3, 3, 2, 2, 1, 1, 1, 4, 4, 4 } }
|
|
#define SUN8I_H5_AC_DELAYS \
|
|
{ 0, 0, 5, 5, 0, 0, 0, 0, \
|
|
0, 0, 0, 0, 3, 3, 3, 3, \
|
|
3, 3, 3, 3, 3, 3, 3, 3, \
|
|
3, 3, 3, 3, 2, 0, 0 }
|
|
|
|
unsigned long sunxi_dram_init(void)
|
|
{
|
|
struct sunxi_mctl_com_reg * const mctl_com =
|
|
(struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
|
|
struct sunxi_mctl_ctl_reg * const mctl_ctl =
|
|
(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
|
|
|
|
struct dram_para para = {
|
|
.dual_rank = 0,
|
|
.bus_width = 32,
|
|
.row_bits = 15,
|
|
.page_size = 4096,
|
|
|
|
#if defined(CONFIG_MACH_SUN8I_H3)
|
|
.dx_read_delays = SUN8I_H3_DX_READ_DELAYS,
|
|
.dx_write_delays = SUN8I_H3_DX_WRITE_DELAYS,
|
|
.ac_delays = SUN8I_H3_AC_DELAYS,
|
|
#elif defined(CONFIG_MACH_SUN50I)
|
|
.dx_read_delays = SUN50I_A64_DX_READ_DELAYS,
|
|
.dx_write_delays = SUN50I_A64_DX_WRITE_DELAYS,
|
|
.ac_delays = SUN50I_A64_AC_DELAYS,
|
|
#elif defined(CONFIG_MACH_SUN50I_H5)
|
|
.dx_read_delays = SUN8I_H5_DX_READ_DELAYS,
|
|
.dx_write_delays = SUN8I_H5_DX_WRITE_DELAYS,
|
|
.ac_delays = SUN8I_H5_AC_DELAYS,
|
|
#endif
|
|
};
|
|
/*
|
|
* Let the compiler optimize alternatives away by passing this value into
|
|
* the static functions. This saves us #ifdefs, but still keeps the binary
|
|
* small.
|
|
*/
|
|
#if defined(CONFIG_MACH_SUN8I_H3)
|
|
uint16_t socid = SOCID_H3;
|
|
#elif defined(CONFIG_MACH_SUN50I)
|
|
uint16_t socid = SOCID_A64;
|
|
#elif defined(CONFIG_MACH_SUN50I_H5)
|
|
uint16_t socid = SOCID_H5;
|
|
#endif
|
|
|
|
mctl_sys_init(socid, ¶);
|
|
if (mctl_channel_init(socid, ¶))
|
|
return 0;
|
|
|
|
if (para.dual_rank)
|
|
writel(0x00000303, &mctl_ctl->odtmap);
|
|
else
|
|
writel(0x00000201, &mctl_ctl->odtmap);
|
|
udelay(1);
|
|
|
|
/* odt delay */
|
|
if (socid == SOCID_H3)
|
|
writel(0x0c000400, &mctl_ctl->odtcfg);
|
|
|
|
if (socid == SOCID_A64 || socid == SOCID_H5) {
|
|
setbits_le32(&mctl_ctl->vtfcr,
|
|
(socid == SOCID_H5 ? 3 : 2) << 8);
|
|
clrbits_le32(&mctl_ctl->pgcr[2], (1 << 13));
|
|
}
|
|
|
|
/* clear credit value */
|
|
setbits_le32(&mctl_com->cccr, 1 << 31);
|
|
udelay(10);
|
|
|
|
mctl_auto_detect_dram_size(¶);
|
|
mctl_set_cr(¶);
|
|
|
|
return (1UL << (para.row_bits + 3)) * para.page_size *
|
|
(para.dual_rank ? 2 : 1);
|
|
}
|