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https://github.com/brain-hackers/u-boot-brain
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f7cf291aa7
The SAMA5D2 has a second internal SRAM that can be reassigned as a L2 cache memory. Make sure it is configured as a L2 cache memory when booting from a SPL image. Based on the commit b5ea95ef2b5b from the at91bootstrap repository. Signed-off-by: Samuel Mescoff <samuel.mescoff@mobile-devices.fr> Reviewed-by: Wenyou Yang <wenyou.yang@atmel.com> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
29 lines
643 B
C
29 lines
643 B
C
/*
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* Copyright (C) 2015 Atmel Corporation
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* Wenyou Yang <wenyou.yang@atmel.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sama5_sfr.h>
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void redirect_int_from_saic_to_aic(void)
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{
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struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
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u32 key32;
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if (!(readl(&sfr->aicredir) & ATMEL_SFR_AICREDIR_NSAIC)) {
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key32 = readl(&sfr->sn1) ^ ATMEL_SFR_AICREDIR_KEY;
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writel((key32 | ATMEL_SFR_AICREDIR_NSAIC), &sfr->aicredir);
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}
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}
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void configure_2nd_sram_as_l2_cache(void)
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{
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struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
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writel(1, &sfr->l2cc_hramc);
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}
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