mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-14 15:16:16 +09:00
30c41d2191
Validates PPA, MC, DPC, Bootscript, DPL and Kernel images in ESBC phase using esbc_validate command. Enable validation of boot.scr script prior to its execution dependent on "secureboot" flag in environment Add header address for PPA to be validated during ESBC phase for LS1088A platform based on LAyerscape Chasis 3. Moves sec_init prior to ppa_init as for validation of PPA sec must be initialised before the PPA is initialised. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Signed-off-by: Vinitha Pillai-B57223 <vinitha.pillai@nxp.com> Signed-off-by: Sumit Garg <sumit.garg@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
247 lines
7.5 KiB
C
247 lines
7.5 KiB
C
/*
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* Copyright 2017 NXP
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef __LS1088_COMMON_H
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#define __LS1088_COMMON_H
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#define CONFIG_REMAKE_ELF
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#define CONFIG_FSL_LAYERSCAPE
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#define CONFIG_MP
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#include <asm/arch/stream_id_lsch3.h>
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#include <asm/arch/config.h>
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#include <asm/arch/soc.h>
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/* Link Definitions */
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#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
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/* Link Definitions */
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#ifdef CONFIG_SPL
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#define CONFIG_SYS_TEXT_BASE 0x80400000
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#else
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#ifdef CONFIG_QSPI_BOOT
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#define CONFIG_SYS_TEXT_BASE 0x20100000
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#else
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#define CONFIG_SYS_TEXT_BASE 0x30100000
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#endif
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#endif
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#define CONFIG_SUPPORT_RAW_INITRD
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#define CONFIG_SKIP_LOWLEVEL_INIT
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#if !defined(CONFIG_SD_BOOT)
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#define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
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#endif
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#define CONFIG_VERY_BIG_RAM
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#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
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#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
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#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
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#define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
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#define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
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/*
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* SMP Definitinos
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*/
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#define CPU_RELEASE_ADDR secondary_boot_func
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#ifdef CONFIG_PCI
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#define CONFIG_CMD_PCI
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#endif
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/* Size of malloc() pool */
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#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
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/* I2C */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */
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/* Serial Port */
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#define CONFIG_CONS_INDEX 1
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#define CONFIG_SYS_NS16550_SERIAL
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#define CONFIG_SYS_NS16550_REG_SIZE 1
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#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
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#define CONFIG_BAUDRATE 115200
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#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
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/* IFC */
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#define CONFIG_FSL_IFC
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/*
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* During booting, IFC is mapped at the region of 0x30000000.
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* But this region is limited to 256MB. To accommodate NOR, promjet
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* and FPGA. This region is divided as below:
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* 0x30000000 - 0x37ffffff : 128MB : NOR flash
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* 0x38000000 - 0x3BFFFFFF : 64MB : Promjet
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* 0x3C000000 - 0x40000000 : 64MB : FPGA etc
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*
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* To accommodate bigger NOR flash and other devices, we will map IFC
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* chip selects to as below:
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* 0x5_1000_0000..0x5_1fff_ffff Memory Hole
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* 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
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* 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
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* 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
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* 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
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*
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* For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
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* CONFIG_SYS_FLASH_BASE has the final address (core view)
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* CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
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* CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
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* CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
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*/
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#define CONFIG_SYS_FLASH_BASE 0x580000000ULL
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#define CONFIG_SYS_FLASH_BASE_PHYS 0x80000000
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#define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
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#define CONFIG_SYS_FLASH1_BASE_PHYS 0xC0000000
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#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY 0x8000000
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#ifndef __ASSEMBLY__
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unsigned long long get_qixis_addr(void);
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#endif
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#define QIXIS_BASE get_qixis_addr()
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#define QIXIS_BASE_PHYS 0x20000000
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#define QIXIS_BASE_PHYS_EARLY 0xC000000
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#define CONFIG_SYS_NAND_BASE 0x530000000ULL
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#define CONFIG_SYS_NAND_BASE_PHYS 0x30000000
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/* MC firmware */
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/* TODO Actual DPL max length needs to be confirmed with the MC FW team */
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#define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET 0x00F00000
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#define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH 0x20000
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#define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET 0x00F20000
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#define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH 0x200000
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#define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET 0x07000000
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/* Define phy_reset function to boot the MC based on mcinitcmd.
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* This happens late enough to properly fixup u-boot env MAC addresses.
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*/
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#define CONFIG_RESET_PHY_R
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/*
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* Carve out a DDR region which will not be used by u-boot/Linux
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*
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* It will be used by MC and Debug Server. The MC region must be
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* 512MB aligned, so the min size to hide is 512MB.
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*/
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#if defined(CONFIG_FSL_MC_ENET)
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#define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE (512UL * 1024 * 1024)
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#endif
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/* Command line configuration */
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#define CONFIG_CMD_GREPENV
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#define CONFIG_CMD_CACHE
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/* Miscellaneous configurable options */
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#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
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/* SATA */
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#ifdef CONFIG_SCSI
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#define CONFIG_LIBATA
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#define CONFIG_SCSI_AHCI
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#define CONFIG_SCSI_AHCI_PLAT
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#define CONFIG_SYS_SATA1 AHCI_BASE_ADDR1
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#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
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#define CONFIG_SYS_SCSI_MAX_LUN 1
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#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
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CONFIG_SYS_SCSI_MAX_LUN)
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#endif
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/* Physical Memory Map */
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#define CONFIG_CHIP_SELECTS_PER_CTRL 4
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#define CONFIG_NR_DRAM_BANKS 2
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#define CONFIG_HWCONFIG
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#define HWCONFIG_BUFFER_SIZE 128
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/* #define CONFIG_DISPLAY_CPUINFO */
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/* Allow to overwrite serial and ethaddr */
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#define CONFIG_ENV_OVERWRITE
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/* Initial environment variables */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"hwconfig=fsl_ddr:bank_intlv=auto\0" \
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"loadaddr=0x80100000\0" \
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"kernel_addr=0x100000\0" \
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"ramdisk_addr=0x800000\0" \
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"ramdisk_size=0x2000000\0" \
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"fdt_high=0xa0000000\0" \
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"initrd_high=0xffffffffffffffff\0" \
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"kernel_start=0x581000000\0" \
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"kernel_load=0xa0000000\0" \
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"kernel_size=0x2800000\0" \
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"console=ttyAMA0,38400n8\0" \
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"mcinitcmd=fsl_mc start mc 0x580a00000" \
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" 0x580e00000 \0"
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#define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
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"earlycon=uart8250,mmio,0x21c0500 " \
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"ramdisk_size=0x3000000 default_hugepagesz=2m" \
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" hugepagesz=2m hugepages=256"
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#if defined(CONFIG_QSPI_BOOT)
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#define CONFIG_BOOTCOMMAND "sf probe 0:0;" \
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"sf read 0x80200000 0xd00000 0x100000;"\
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" fsl_mc apply dpl 0x80200000 &&" \
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" sf read $kernel_load $kernel_start" \
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" $kernel_size && bootm $kernel_load"
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#elif defined(CONFIG_SD_BOOT)
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#define CONFIG_BOOTCOMMAND "mmcinfo;mmc read 0x80200000 0x6800 0x800;"\
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" fsl_mc apply dpl 0x80200000 &&" \
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" mmc read $kernel_load $kernel_start" \
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" $kernel_size && bootm $kernel_load"
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#else /* NOR BOOT*/
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#define CONFIG_BOOTCOMMAND "fsl_mc apply dpl 0x580d00000 &&" \
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" cp.b $kernel_start $kernel_load" \
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" $kernel_size && bootm $kernel_load"
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#endif
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/* Monitor Command Prompt */
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#define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
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#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
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sizeof(CONFIG_SYS_PROMPT) + 16)
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#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
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#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
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#define CONFIG_SYS_LONGHELP
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#define CONFIG_CMDLINE_EDITING 1
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#define CONFIG_AUTO_COMPLETE
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#define CONFIG_SYS_MAXARGS 64 /* max command args */
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#define CONFIG_PANIC_HANG /* do not reset board on panic */
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#ifdef CONFIG_SPL
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#define CONFIG_SPL_BSS_START_ADDR 0x80100000
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#define CONFIG_SPL_BSS_MAX_SIZE 0x00100000
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#define CONFIG_SPL_FRAMEWORK
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#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
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#define CONFIG_SPL_MAX_SIZE 0x16000
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#define CONFIG_SPL_STACK (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
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#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
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#define CONFIG_SPL_TEXT_BASE 0x1800a000
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000
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#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
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#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
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#endif
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#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
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#endif /* __LS1088_COMMON_H */
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