mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-07 18:53:45 +09:00
32cccecd06
icache is already enabled by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
151 lines
2.7 KiB
C
151 lines
2.7 KiB
C
/*
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* (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <netdev.h>
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#include <zynqpl.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Bootmode setting values */
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#define ZYNQ_BM_MASK 0x0F
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#define ZYNQ_BM_NOR 0x02
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#define ZYNQ_BM_SD 0x05
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#define ZYNQ_BM_JTAG 0x0
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#ifdef CONFIG_FPGA
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Xilinx_desc fpga;
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/* It can be done differently */
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Xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
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Xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
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Xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
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Xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
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Xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
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Xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
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#endif
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int board_init(void)
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{
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#ifdef CONFIG_FPGA
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u32 idcode;
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idcode = zynq_slcr_get_idcode();
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switch (idcode) {
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case XILINX_ZYNQ_7010:
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fpga = fpga010;
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break;
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case XILINX_ZYNQ_7015:
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fpga = fpga015;
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break;
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case XILINX_ZYNQ_7020:
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fpga = fpga020;
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break;
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case XILINX_ZYNQ_7030:
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fpga = fpga030;
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break;
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case XILINX_ZYNQ_7045:
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fpga = fpga045;
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break;
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case XILINX_ZYNQ_7100:
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fpga = fpga100;
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break;
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}
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#endif
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#ifdef CONFIG_FPGA
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fpga_init();
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fpga_add(fpga_xilinx, &fpga);
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#endif
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return 0;
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}
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int board_late_init(void)
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{
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switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
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case ZYNQ_BM_NOR:
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setenv("modeboot", "norboot");
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break;
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case ZYNQ_BM_SD:
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setenv("modeboot", "sdboot");
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break;
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case ZYNQ_BM_JTAG:
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setenv("modeboot", "jtagboot");
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break;
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default:
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setenv("modeboot", "");
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break;
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}
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return 0;
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}
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#ifdef CONFIG_CMD_NET
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int board_eth_init(bd_t *bis)
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{
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u32 ret = 0;
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#ifdef CONFIG_XILINX_AXIEMAC
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ret |= xilinx_axiemac_initialize(bis, XILINX_AXIEMAC_BASEADDR,
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XILINX_AXIDMA_BASEADDR);
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#endif
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#ifdef CONFIG_XILINX_EMACLITE
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u32 txpp = 0;
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u32 rxpp = 0;
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# ifdef CONFIG_XILINX_EMACLITE_TX_PING_PONG
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txpp = 1;
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# endif
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# ifdef CONFIG_XILINX_EMACLITE_RX_PING_PONG
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rxpp = 1;
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# endif
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ret |= xilinx_emaclite_initialize(bis, XILINX_EMACLITE_BASEADDR,
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txpp, rxpp);
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#endif
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#if defined(CONFIG_ZYNQ_GEM)
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# if defined(CONFIG_ZYNQ_GEM0)
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ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR0,
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CONFIG_ZYNQ_GEM_PHY_ADDR0, 0);
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# endif
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# if defined(CONFIG_ZYNQ_GEM1)
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ret |= zynq_gem_initialize(bis, ZYNQ_GEM_BASEADDR1,
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CONFIG_ZYNQ_GEM_PHY_ADDR1, 0);
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# endif
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#endif
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return ret;
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}
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#endif
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#ifdef CONFIG_CMD_MMC
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int board_mmc_init(bd_t *bd)
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{
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int ret = 0;
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#if defined(CONFIG_ZYNQ_SDHCI)
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# if defined(CONFIG_ZYNQ_SDHCI0)
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ret = zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR0);
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# endif
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# if defined(CONFIG_ZYNQ_SDHCI1)
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ret |= zynq_sdhci_init(ZYNQ_SDHCI_BASEADDR1);
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# endif
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#endif
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return ret;
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}
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#endif
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int dram_init(void)
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{
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gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
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zynq_ddrc_init();
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return 0;
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}
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