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32c8cfb23c
P1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark level register description has been changed: 9-15 bits represent WR_WML[0:6], Max value = 128 represented by 0x00 25-31 bits represent RD_WML[0:6], Max value = 128 represented by 0x00 Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <Poonam.Aggrwal@freescale.com> Tested-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> |
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.. | ||
atmel_mci.c | ||
atmel_mci.h | ||
bfin_sdh.c | ||
davinci_mmc.c | ||
fsl_esdhc.c | ||
gen_atmel_mci.c | ||
Makefile | ||
mmc.c | ||
mxcmmc.c | ||
omap3_mmc.c | ||
omap3_mmc.h | ||
omap_hsmmc.c | ||
pxa_mmc.c | ||
pxa_mmc.h | ||
s5p_mmc.c |