mirror of
https://github.com/brain-hackers/u-boot-brain
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0107f24036
Move arch/arm/cpu/armv7/zynq/* -> arch/arm/mach-zynq/* Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
51 lines
1.4 KiB
C
51 lines
1.4 KiB
C
/*
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* Copyright (C) 2012 - 2013 Michal Simek <monstr@monstr.eu>
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* Copyright (C) 2012 - 2013 Xilinx, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/hardware.h>
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DECLARE_GLOBAL_DATA_PTR;
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/* Control regsiter bitfield definitions */
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#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK 0xC
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#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT 2
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#define ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT 1
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/* ECC scrub regsiter definitions */
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#define ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK 0x7
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#define ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED 0x4
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void zynq_ddrc_init(void)
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{
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u32 width, ecctype;
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width = readl(&ddrc_base->ddrc_ctrl);
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width = (width & ZYNQ_DDRC_CTRLREG_BUSWIDTH_MASK) >>
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ZYNQ_DDRC_CTRLREG_BUSWIDTH_SHIFT;
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ecctype = (readl(&ddrc_base->ecc_scrub) &
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ZYNQ_DDRC_ECC_SCRUBREG_ECC_MODE_MASK);
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/* ECC is enabled when memory is in 16bit mode and it is enabled */
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if ((ecctype == ZYNQ_DDRC_ECC_SCRUBREG_ECCMODE_SECDED) &&
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(width == ZYNQ_DDRC_CTRLREG_BUSWIDTH_16BIT)) {
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puts("ECC enabled ");
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/*
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* Clear the first 1MB because it is not initialized from
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* first stage bootloader. To get ECC to work all memory has
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* been initialized by writing any value.
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*/
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/* cppcheck-suppress nullPointer */
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memset((void *)0, 0, 1 * 1024 * 1024);
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gd->ram_size /= 2;
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} else {
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puts("ECC disabled ");
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}
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}
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