mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
3da428595e
This patch adds the DDR calibration portion of the Altera SDRAM driver. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
269 lines
2.6 KiB
C
269 lines
2.6 KiB
C
/*
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* Copyright Altera Corporation (C) 2012-2015
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifdef CONFIG_SOCFPGA_ARRIA5
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/* The if..else... is not required if generated by tools */
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const u32 inst_rom_init[] = {
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0x80000,
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0x80680,
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0x8180,
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0x8200,
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0x8280,
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0x8300,
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0x8380,
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0x8100,
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0x8480,
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0x8500,
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0x8580,
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0x8600,
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0x8400,
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0x800,
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0x8680,
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0x880,
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0xa680,
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0x80680,
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0x900,
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0x80680,
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0x980,
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0x8680,
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0x80680,
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0xb68,
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0xcce8,
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0xae8,
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0x8ce8,
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0xb88,
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0xec88,
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0xa08,
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0xac88,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x60e80,
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0x61080,
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0x61080,
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0x61080,
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0xa680,
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0x8680,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x70e80,
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0x71080,
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0x71080,
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0x71080,
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0xa680,
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0x8680,
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0x80680,
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0x1158,
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0x6d8,
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0x80680,
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0x1168,
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0x7e8,
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0x7e8,
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0x87e8,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x1168,
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0x7e8,
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0x7e8,
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0xa7e8,
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0x80680,
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0x40e88,
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0x41088,
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0x41088,
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0x41088,
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0x40f68,
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0x410e8,
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0x410e8,
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0x410e8,
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0xa680,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x41008,
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0x41088,
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0x41088,
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0x41088,
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0x1100,
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0xc680,
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0x8680,
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0xe680,
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0x80680,
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0x0,
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0x8000,
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0xa000,
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0xc000,
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0x80000,
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0x80,
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0x8080,
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0xa080,
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0xc080,
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0x80080,
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0x9180,
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0x8680,
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0xa680,
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0x80680,
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0x40f08,
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0x80680
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};
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#else
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const u32 inst_rom_init[] = {
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0x80000,
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0x80680,
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0x8180,
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0x8200,
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0x8280,
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0x8300,
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0x8380,
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0x8100,
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0x8480,
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0x8500,
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0x8580,
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0x8600,
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0x8400,
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0x800,
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0x8680,
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0x880,
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0xa680,
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0x80680,
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0x900,
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0x80680,
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0x980,
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0x8680,
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0x80680,
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0xb68,
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0xcce8,
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0xae8,
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0x8ce8,
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0xb88,
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0xec88,
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0xa08,
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0xac88,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0x20ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x60e80,
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0x61080,
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0x61080,
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0x61080,
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0xa680,
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0x8680,
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0x80680,
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0xce00,
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0xcd80,
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0xe700,
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0xc00,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0x30ce0,
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0xd00,
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0x680,
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0x680,
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0x680,
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0x680,
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0x70e80,
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0x71080,
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0x71080,
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0x71080,
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0xa680,
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0x8680,
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0x80680,
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0x1158,
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0x6d8,
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0x80680,
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0x1168,
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0x7e8,
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0x7e8,
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0x87e8,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x1168,
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0x7e8,
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0x7e8,
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0xa7e8,
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0x80680,
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0x40e88,
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0x41088,
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0x41088,
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0x41088,
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0x40f68,
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0x410e8,
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0x410e8,
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0x410e8,
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0xa680,
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0x40fe8,
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0x410e8,
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0x410e8,
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0x410e8,
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0x41008,
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0x41088,
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0x41088,
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0x41088,
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0x1100,
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0xc680,
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0x8680,
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0xe680,
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0x80680,
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0x0,
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0x0,
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0xa000,
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0x8000,
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0x80000,
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0x80,
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0x80,
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0x80,
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0x80,
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0xa080,
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0x8080,
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0x80080,
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0x9180,
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0x8680,
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0xa680,
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0x80680,
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0x40f08,
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0x80680
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};
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#endif /* CONFIG_SOCFPGA_ARRIA5 */
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