mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-23 19:39:44 +09:00
c33aa3527d
At present the APs (non-boot CPUs) are inited once and then parked ready for the OS to use them. However in some cases we want to send new requests through, such as to change MTRRs and keep them consistent across CPUs. Change the last state of the flight plan to go into a wait loop, accepting instructions from the main CPU. Drop cpu_map since it is not used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
104 lines
2.1 KiB
Plaintext
104 lines
2.1 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0
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#
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# Copyright 2019 Google LLC
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#
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config INTEL_APOLLOLAKE
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bool
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select FSP_VERSION2
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select HAVE_FSP
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select ARCH_MISC_INIT
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select USE_CAR
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select INTEL_PMC
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select TPL_X86_TSC_TIMER_NATIVE
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select SPL_PCH_SUPPORT
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select TPL_PCH_SUPPORT
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select PCH_SUPPORT
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select P2SB
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select SMP_AP_WORK
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imply ENABLE_MRC_CACHE
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imply AHCI_PCI
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imply SCSI
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imply SCSI_AHCI
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imply SPI_FLASH
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imply USB
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imply USB_EHCI_HCD
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imply TPL
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imply SPL
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imply TPL_X86_16BIT_INIT
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imply TPL_OF_PLATDATA
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imply ACPI_PMC
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imply MMC
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imply DM_MMC
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imply MMC_PCI
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imply MMC_SDHCI
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imply CMD_MMC
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imply VIDEO_FSP
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imply PINCTRL_INTEL
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imply PINCTRL_INTEL_APL
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imply HAVE_VBT
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imply HAVE_X86_FIT
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imply INTEL_GPIO
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imply SMP
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imply HAVE_ITSS
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imply HAVE_P2SB
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imply CLK
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imply CMD_CLK
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imply CLK_INTEL
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imply ACPI_GPE
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if INTEL_APOLLOLAKE
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config DCACHE_RAM_BASE
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default 0xfef00000
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config DCACHE_RAM_SIZE
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default 0xc0000
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config DCACHE_RAM_MRC_VAR_SIZE
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default 0xb0000
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config CPU_SPECIFIC_OPTIONS
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def_bool y
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select SMM_TSEG
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select X86_RAMTEST
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config SMM_TSEG_SIZE
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hex
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default 0x800000
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config MMCONF_BASE_ADDRESS
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hex
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default 0xe0000000
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config TPL_SIZE_LIMIT
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default 0x7800
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config CPU_ADDR_BITS
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default 39
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config APL_SPI_FLASH_BOOT
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bool "Support booting with SPI-flash driver instead memory-mapped SPI"
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select TPL_SPI_FLASH_SUPPORT
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select TPL_SPI_SUPPORT
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help
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This enables SPI and SPI flash in TPL. Without the this only
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available boot method is to use memory-mapped SPI. Since this is
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actually fast and produces a TPL which is 7KB smaller, memory-mapped
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SPI is the default.
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config APL_BOOT_FROM_FAST_SPI_FLASH
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bool "Boot using SPI flash driver"
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select APL_SPI_FLASH_BOOT
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help
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This option is separate from APL_SPI_FLASH_BOOT since it is useful to
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be able to compare booting speed with the same build. Enable this to
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use the SPI-flash driver to load SPL, U-Boot and FSP-M. For technical
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reasons FSP-S is currently always loaded from memory-mapped SPI. See
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Apollo Lake's arch_fsp_init_r() for details about that.
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config VBT_ADDR
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default 0xff3f1000
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endif
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