mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
67482f57e6
ARC HS Development Kit board is a new low-cost
development platform sporting ARC HS38 in real silicon
with nice set of features such as:
* Quad-core ARC HS38 with 512 kB L2 cache and running @1GHz
* 4Gb of DDR (we use only lowest 1Gb out of it now)
* Lots of DesigWare peripherals
* Different connectivity modules:
- Synopsys HAPS HT3
- Arduino-compatible connector
- MikroBUS
This initial commit supports the following peripherals:
* UART (DW 8250)
* Ethernet (DW GMAC)
* SD/MMC (DW Mobile Storage)
* USB 1.1 & 2.0
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
/*
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* Copyright (C) 2017 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <dwmmc.h>
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#include <malloc.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define CREG_BASE (ARC_PERIPHERAL_BASE + 0x1000)
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#define CREG_PAE (CREG_BASE + 0x180)
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#define CREG_PAE_UPDATE (CREG_BASE + 0x194)
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#define CREG_CPU_START (CREG_BASE + 0x400)
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int board_early_init_f(void)
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{
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/* In current chip PAE support for DMA is broken, disabling it. */
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writel(0, (void __iomem *) CREG_PAE);
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/* Really apply settings made above */
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writel(1, (void __iomem *) CREG_PAE_UPDATE);
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return 0;
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}
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int board_mmc_init(bd_t *bis)
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{
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struct dwmci_host *host = NULL;
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host = malloc(sizeof(struct dwmci_host));
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if (!host) {
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printf("dwmci_host malloc fail!\n");
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return 1;
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}
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memset(host, 0, sizeof(struct dwmci_host));
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host->name = "Synopsys Mobile storage";
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host->ioaddr = (void *)ARC_DWMMC_BASE;
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host->buswidth = 4;
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host->dev_index = 0;
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host->bus_hz = 100000000;
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add_dwmci(host, host->bus_hz / 2, 400000);
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return 0;
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}
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#define RESET_VECTOR_ADDR 0x0
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void smp_set_core_boot_addr(unsigned long addr, int corenr)
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{
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/* All cores have reset vector pointing to 0 */
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writel(addr, (void __iomem *)RESET_VECTOR_ADDR);
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/* Make sure other cores see written value in memory */
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flush_dcache_all();
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}
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void smp_kick_all_cpus(void)
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{
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#define BITS_START_CORE1 1
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#define BITS_START_CORE2 2
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#define BITS_START_CORE3 3
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int cmd = readl((void __iomem *)CREG_CPU_START);
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cmd |= (1 << BITS_START_CORE1) |
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(1 << BITS_START_CORE2) |
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(1 << BITS_START_CORE3);
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writel(cmd, (void __iomem *)CREG_CPU_START);
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}
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