mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-19 19:23:21 +09:00
89f44bb0ce
This patch adds the DDR3 ECC support to enable ECC in the DDR3 EMIF controller for Keystone II devices. By default, ECC will only be enabled if RMW is supported in the DDR EMIF controller. The entire DDR memory will be scrubbed to zero using an EDMA channel after ECC is enabled and before u-boot is re-located to DDR memory. An ecc_test environment variable is added for ECC testing. If ecc_test is set to 0, a detection of 2-bit error will reset the device, if ecc_test is set to 1, 2-bit error detection will not reset the device, user can still boot the kernel to check the ECC error handling in kernel. Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
64 lines
1.3 KiB
C
64 lines
1.3 KiB
C
/*
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* DDR3
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*
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* (C) Copyright 2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _DDR3_H_
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#define _DDR3_H_
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#include <asm/arch/hardware.h>
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struct ddr3_phy_config {
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unsigned int pllcr;
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unsigned int pgcr1_mask;
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unsigned int pgcr1_val;
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unsigned int ptr0;
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unsigned int ptr1;
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unsigned int ptr2;
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unsigned int ptr3;
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unsigned int ptr4;
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unsigned int dcr_mask;
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unsigned int dcr_val;
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unsigned int dtpr0;
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unsigned int dtpr1;
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unsigned int dtpr2;
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unsigned int mr0;
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unsigned int mr1;
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unsigned int mr2;
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unsigned int dtcr;
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unsigned int pgcr2;
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unsigned int zq0cr1;
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unsigned int zq1cr1;
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unsigned int zq2cr1;
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unsigned int pir_v1;
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unsigned int pir_v2;
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};
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struct ddr3_emif_config {
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unsigned int sdcfg;
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unsigned int sdtim1;
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unsigned int sdtim2;
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unsigned int sdtim3;
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unsigned int sdtim4;
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unsigned int zqcfg;
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unsigned int sdrfc;
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};
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void ddr3_init(void);
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int ddr3_get_size(void);
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void ddr3_reset_ddrphy(void);
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void ddr3_init_ecc(u32 base);
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void ddr3_disable_ecc(u32 base);
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void ddr3_check_ecc_int(u32 base);
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int ddr3_ecc_support_rmw(u32 base);
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void ddr3_err_reset_workaround(void);
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void ddr3_enable_ecc(u32 base, int test);
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void ddr3_init_ddrphy(u32 base, struct ddr3_phy_config *phy_cfg);
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void ddr3_init_ddremif(u32 base, struct ddr3_emif_config *emif_cfg);
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#endif
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