mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-06 11:16:15 +09:00
9017d9325a
The Nand flash was unable to read and write properly due to Nand Chip Select (nCE) setup was in reverse order. Also, increase the Nand time out value to 60. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
94 lines
2.3 KiB
C
94 lines
2.3 KiB
C
/*
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* (C) Copyright 2000-2003
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*
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* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
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* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <common.h>
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#include <asm/io.h>
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#include <asm/immap.h>
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_CMD_NAND)
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#include <nand.h>
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#include <linux/mtd/mtd.h>
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#define SET_CLE 0x10
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#define SET_ALE 0x08
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static void nand_hwcontrol(struct mtd_info *mtdinfo, int cmd, unsigned int ctrl)
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{
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struct nand_chip *this = mtdinfo->priv;
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volatile u16 *nCE = (u16 *) CONFIG_SYS_LATCH_ADDR;
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if (ctrl & NAND_CTRL_CHANGE) {
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ulong IO_ADDR_W = (ulong) this->IO_ADDR_W;
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IO_ADDR_W &= ~(SET_ALE | SET_CLE);
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if (ctrl & NAND_NCE)
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*nCE &= 0xFFFB;
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else
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*nCE |= 0x0004;
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if (ctrl & NAND_CLE)
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IO_ADDR_W |= SET_CLE;
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if (ctrl & NAND_ALE)
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IO_ADDR_W |= SET_ALE;
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this->IO_ADDR_W = (void *)IO_ADDR_W;
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}
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if (cmd != NAND_CMD_NONE)
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writeb(cmd, this->IO_ADDR_W);
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}
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int board_nand_init(struct nand_chip *nand)
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{
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volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
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volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
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fbcs->csmr2 &= ~FBCS_CSMR_WP;
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/*
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* set up pin configuration - enabled 2nd output buffer's signals
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* (nand_ngpio - nCE USB1/2_PWR_EN, LATCH_GPIOs, LCD_VEEEN, etc)
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* to use nCE signal
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*/
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gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
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gpio->pddr_timer |= 0x08;
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gpio->ppd_timer |= 0x08;
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gpio->pclrr_timer = 0;
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gpio->podr_timer = 0;
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nand->chip_delay = 60;
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nand->ecc.mode = NAND_ECC_SOFT;
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nand->cmd_ctrl = nand_hwcontrol;
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return 0;
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}
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#endif
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