Rick Chen 8ba595b6bd riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL ... The mcache_ctl csr only can be manipulated in M mode. Add SPL_RISCV_MMODE for U-Boot SPL to control cache operation. Signed-off-by: Rick Chen <rick@andestech.com> Cc: KC Lin <kclin@andestech.com> Cc: Alan Kao <alankao@andestech.com>		2019-12-10 08:23:10 +08:00
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cpu	riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL	2019-12-10 08:23:10 +08:00
dts	riscv: dts: Add hifive-unleashed-a00 dts from Linux	2019-12-10 08:23:10 +08:00
include/asm	gpio: sifive: add support for DM based gpio driver for FU540-SoC	2019-10-18 09:04:01 +08:00
lib	riscv: andes_plic: Fix some wrong configurations	2019-12-10 08:23:10 +08:00
config.mk	riscv: qemu: define standalone load address	2019-01-15 09:36:31 +08:00
Kconfig	riscv: increase stack size to avoid a stack overflow during distro boot	2019-12-10 08:23:10 +08:00
Makefile	riscv: add Kconfig entries for the code model	2018-12-18 09:56:26 +08:00