mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-11 21:56:21 +09:00
35fe948e3b
The BSC9132 is a highly integrated device that targets the evolving
Microcell, Picocell, and Enterprise-Femto base station market subsegments.
The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
core technologies with MAPLE-B2P baseband acceleration processing elements
to address the need for a high performance, low cost, integrated solution
that handles all required processing layers without the need for an
external device except for an RF transceiver or, in a Micro base station
configuration, a host device that handles the L3/L4 and handover between
sectors.
The BSC9132 SoC includes the following function and features:
- Power Architecture subsystem including two e500 processors with
512-Kbyte shared L2 cache
- Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
cache
- 32 Kbyte of shared M3 memory
- The Multi Accelerator Platform Engine for Pico BaseStation Baseband
Processing (MAPLE-B2P)
- Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
ECC), up to 1333 MHz data rate
- Dedicated security engine featuring trusted boot
- Two DMA controllers
- OCNDMA with four bidirectional channels
- SysDMA with sixteen bidirectional channels
- Interfaces
- Four-lane SerDes PHY
- PCI Express controller complies with the PEX Specification-Rev 2.0
- Two Common Public Radio Interface (CPRI) controller lanes
- High-speed USB 2.0 host and device controller with ULPI interface
- Enhanced secure digital (SD/MMC) host controller (eSDHC)
- Antenna interface controller (AIC), supporting four industry
standard JESD207/four custom ADI RF interfaces
- ADI lanes support both full duplex FDD support & half duplex TDD
- Universal Subscriber Identity Module (USIM) interface that
facilitates communication to SIM cards or Eurochip pre-paid phone
cards
- Two DUART, two eSPI, and two I2C controllers
- Integrated Flash memory controller (IFC)
- GPIO
- Sixteen 32-bit timers
Signed-off-by: Naveen Burmi <NaveenBurmi@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
598 lines
21 KiB
C
598 lines
21 KiB
C
/*
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* Copyright 2011-2012 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#ifndef _ASM_MPC85xx_CONFIG_H_
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#define _ASM_MPC85xx_CONFIG_H_
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/* SoC specific defines for Freescale MPC85xx (PQ3) and QorIQ processors */
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#ifdef CONFIG_SYS_CCSRBAR_DEFAULT
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#error "Do not define CONFIG_SYS_CCSRBAR_DEFAULT in the board header file."
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#endif
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/*
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* This macro should be removed when we no longer care about backwards
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* compatibility with older operating systems.
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*/
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#define CONFIG_PPC_SPINTABLE_COMPATIBLE
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#define FSL_DDR_VER_4_7 47
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/* Number of TLB CAM entries we have on FSL Book-E chips */
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#if defined(CONFIG_E500MC)
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#define CONFIG_SYS_NUM_TLBCAMS 64
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#elif defined(CONFIG_E500)
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#define CONFIG_SYS_NUM_TLBCAMS 16
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#endif
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#if defined(CONFIG_MPC8536)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 1
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8540)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8541)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8544)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8548)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 0
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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#define CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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#define CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_MPC8555)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8560)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 8
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#elif defined(CONFIG_MPC8568)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x10000UL
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#define MAX_QE_RISC 2
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#define QE_NUM_OF_SNUM 28
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_MPC8569)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 10
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define QE_MURAM_SIZE 0x20000UL
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#define MAX_QE_RISC 4
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#define QE_NUM_OF_SNUM 46
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_MPC8572)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_DDR_115
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#define CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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#elif defined(CONFIG_P1010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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/* P1011 is single core version of P1020 */
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#elif defined(CONFIG_P1011)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1012 is single core version of P1021 */
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#elif defined(CONFIG_P1012)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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/* P1013 is single core version of P1022 */
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#elif defined(CONFIG_P1013)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#elif defined(CONFIG_P1014)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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#define CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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/* P1017 is single core version of P1023 */
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#elif defined(CONFIG_P1017)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 2
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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#elif defined(CONFIG_P1020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#elif defined(CONFIG_P1021)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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#elif defined(CONFIG_P1022)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_FSL_SATA_ERRATUM_A001
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#elif defined(CONFIG_P1023)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 2
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_QMAN_NUM_PORTALS 3
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#define CONFIG_SYS_BMAN_NUM_PORTALS 3
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#define CONFIG_SYS_FM_MURAM_SIZE 0x10000
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff600000
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/* P1024 is lower end variant of P1020 */
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#elif defined(CONFIG_P1024)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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/* P1025 is lower end variant of P1021 */
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#elif defined(CONFIG_P1025)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_TSECV2
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#define CONFIG_FSL_PCIE_DISABLE_ASPM
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define QE_MURAM_SIZE 0x6000UL
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#define MAX_QE_RISC 1
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#define QE_NUM_OF_SNUM 28
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/* P2010 is single core version of P2020 */
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#elif defined(CONFIG_P2010)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#elif defined(CONFIG_P2020)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
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#define CONFIG_SYS_FSL_SEC_COMPAT 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#elif defined(CONFIG_PPC_P2041) /* also supports P2040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#elif defined(CONFIG_PPC_P3041)
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 0x11
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#elif defined(CONFIG_PPC_P4080) /* also supports P4040 */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_MAX_CPUS 8
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 4
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#define CONFIG_SYS_NUM_FM2_DTSEC 4
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_NUM_FM2_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,p4080-pcie"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A002
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#define CONFIG_SYS_FSL_ERRATUM_CPC_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC135
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC13
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#define CONFIG_SYS_P4080_ERRATUM_CPU22
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#define CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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#define CONFIG_SYS_P4080_ERRATUM_SERDES8
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#define CONFIG_SYS_P4080_ERRATUM_SERDES9
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#define CONFIG_SYS_P4080_ERRATUM_SERDES_A001
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#define CONFIG_SYS_P4080_ERRATUM_SERDES_A005
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#define CONFIG_SYS_FSL_ERRATUM_CPU_A003999
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_RMU
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#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x20
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#define CONFIG_SYS_FSL_ERRATUM_A004849
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#define CONFIG_SYS_FSL_ERRATUM_A004580
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#define CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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#elif defined(CONFIG_PPC_P5020) /* also supports P5010 */
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 2
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 1
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 32
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER
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#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xc0000000
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#define CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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#elif defined(CONFIG_PPC_P5040)
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#define CONFIG_SYS_PPC64
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS1
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#define CONFIG_MAX_CPUS 4
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 3
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 5
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#define CONFIG_SYS_NUM_FM1_10GEC 1
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#define CONFIG_SYS_NUM_FM2_DTSEC 5
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#define CONFIG_SYS_NUM_FM2_10GEC 1
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_FM_MURAM_SIZE 0x28000
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#define CONFIG_SYS_FSL_TBCLK_DIV 16
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
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#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
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#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ERRATUM_USB138
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003
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#define CONFIG_SYS_FSL_ERRATUM_DDR_A003474
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#define CONFIG_SYS_FSL_ERRATUM_A004699
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#define CONFIG_SYS_FSL_ERRATUM_A004510
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#define CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV 0x10
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#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
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#elif defined(CONFIG_BSC9131)
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#define CONFIG_MAX_CPUS 1
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_NUM_DDR_CONTROLLERS 1
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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|
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#elif defined(CONFIG_BSC9132)
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#define CONFIG_MAX_CPUS 2
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#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3
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#define CONFIG_FSL_SDHC_V2_3
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#define CONFIG_SYS_FSL_NUM_LAWS 12
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#define CONFIG_TSECV2
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_NUM_DDR_CONTROLLERS 2
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#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
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#define CONFIG_NAND_FSL_IFC
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#define CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
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#define CONFIG_SYS_FSL_ESDHC_P1010_BROKEN_SDCLK
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#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.2"
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|
|
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#elif defined(CONFIG_PPC_T4240)
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#define CONFIG_SYS_PPC64 /* 64-bit core */
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#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
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#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
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#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
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#define CONFIG_MAX_CPUS 12
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#define CONFIG_SYS_FSL_NUM_CC_PLLS 5
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#define CONFIG_SYS_FSL_NUM_LAWS 32
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#define CONFIG_SYS_FSL_SRDS_3
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#define CONFIG_SYS_FSL_SRDS_4
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#define CONFIG_SYS_FSL_SEC_COMPAT 4
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#define CONFIG_SYS_NUM_FMAN 2
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#define CONFIG_SYS_NUM_FM1_DTSEC 8
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#define CONFIG_SYS_NUM_FM1_10GEC 2
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#define CONFIG_SYS_NUM_FM2_DTSEC 8
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#define CONFIG_SYS_NUM_FM2_10GEC 2
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#define CONFIG_NUM_DDR_CONTROLLERS 3
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#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
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|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v3.0"
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|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
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|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
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#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB2_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
|
|
#define CONFIG_SYS_FSL_ERRATUM_A004468
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
#elif defined(CONFIG_PPC_B4420)
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
#define CONFIG_MAX_CPUS 2
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 4
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 1
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
#elif defined(CONFIG_PPC_B4860)
|
|
#define CONFIG_SYS_PPC64 /* 64-bit core */
|
|
#define CONFIG_FSL_CORENET /* Freescale CoreNet platform */
|
|
#define CONFIG_SYS_FSL_QORIQ_CHASSIS2 /* Freescale Chassis generation 2 */
|
|
#define CONFIG_SYS_FSL_QMAN_V3 /* QMAN version 3 */
|
|
#define CONFIG_MAX_CPUS 4
|
|
#define CONFIG_SYS_FSL_NUM_CC_PLLS 4
|
|
#define CONFIG_SYS_FSL_NUM_LAWS 32
|
|
#define CONFIG_SYS_FSL_SEC_COMPAT 4
|
|
#define CONFIG_SYS_NUM_FMAN 1
|
|
#define CONFIG_SYS_NUM_FM1_DTSEC 6
|
|
#define CONFIG_SYS_NUM_FM1_10GEC 2
|
|
#define CONFIG_NUM_DDR_CONTROLLERS 2
|
|
#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_4_7
|
|
#define CONFIG_SYS_FMAN_V3
|
|
#define CONFIG_SYS_FM_MURAM_SIZE 0x60000
|
|
#define CONFIG_SYS_FSL_TBCLK_DIV 16
|
|
#define CONFIG_SYS_FSL_PCIE_COMPAT "fsl,qoriq-pcie-v2.4"
|
|
#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2
|
|
#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9
|
|
#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5
|
|
#define CONFIG_SYS_FSL_USB1_PHY_ENABLE
|
|
#define CONFIG_SYS_FSL_ERRATUM_A_004934
|
|
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
|
|
|
|
#else
|
|
#error Processor type not defined for this platform
|
|
#endif
|
|
|
|
#ifndef CONFIG_SYS_CCSRBAR_DEFAULT
|
|
#error "CONFIG_SYS_CCSRBAR_DEFAULT is not defined for this platform."
|
|
#endif
|
|
|
|
#endif /* _ASM_MPC85xx_CONFIG_H_ */
|