mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-01 15:53:46 +09:00
316fd3920f
Quark SoC holds the PCIe controller in reset following a power on. U-Boot needs to release the PCIe controller from reset. The PCIe controller (D23:F0/F1) will not be visible in PCI configuration space and any access to its PCI configuration registers will cause system hang while it is held in reset. Enable PCIe controller per Quark firmware writer guide. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
172 lines
4.2 KiB
C
172 lines
4.2 KiB
C
/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _QUARK_H_
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#define _QUARK_H_
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/* Message Bus Ports */
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#define MSG_PORT_MEM_ARBITER 0x00
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#define MSG_PORT_HOST_BRIDGE 0x03
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#define MSG_PORT_RMU 0x04
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#define MSG_PORT_MEM_MGR 0x05
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#define MSG_PORT_PCIE_AFE 0x16
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#define MSG_PORT_SOC_UNIT 0x31
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/* Port 0x00: Memory Arbiter Message Port Registers */
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/* Enhanced Configuration Space */
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#define AEC_CTRL 0x00
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/* Port 0x03: Host Bridge Message Port Registers */
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/* Host Miscellaneous Controls 2 */
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#define HMISC2 0x03
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#define HMISC2_SEGE 0x00000002
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#define HMISC2_SEGF 0x00000004
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#define HMISC2_SEGAB 0x00000010
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/* Host Memory I/O Boundary */
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#define HM_BOUND 0x08
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/* Extended Configuration Space */
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#define HEC_REG 0x09
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/* Port 0x04: Remote Management Unit Message Port Registers */
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/* ACPI PBLK Base Address Register */
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#define PBLK_BA 0x70
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/* SPI DMA Base Address Register */
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#define SPI_DMA_BA 0x7a
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/* Port 0x05: Memory Manager Message Port Registers */
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/* eSRAM Block Page Control */
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#define ESRAM_BLK_CTRL 0x82
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#define ESRAM_BLOCK_MODE 0x10000000
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/* Port 0x16: PCIe AFE Unit Port Registers */
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#define PCIE_RXPICTRL0_L0 0x2080
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#define PCIE_RXPICTRL0_L1 0x2180
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/* Port 0x31: SoC Unit Port Registers */
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/* PCIe Controller Config */
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#define PCIE_CFG 0x36
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#define PCIE_CTLR_PRI_RST 0x00010000
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#define PCIE_PHY_SB_RST 0x00020000
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#define PCIE_CTLR_SB_RST 0x00040000
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#define PCIE_PHY_LANE_RST 0x00090000
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#define PCIE_CTLR_MAIN_RST 0x00100000
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/* DRAM */
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#define DRAM_BASE 0x00000000
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#define DRAM_MAX_SIZE 0x80000000
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/* eSRAM */
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#define ESRAM_SIZE 0x80000
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/* Memory BAR Enable */
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#define MEM_BAR_EN 0x00000001
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/* I/O BAR Enable */
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#define IO_BAR_EN 0x80000000
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/* 64KiB of RMU binary in flash */
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#define RMU_BINARY_SIZE 0x10000
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/* Legacy Bridge PCI Configuration Registers */
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#define LB_GBA 0x44
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#define LB_PM1BLK 0x48
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#define LB_GPE0BLK 0x4c
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#define LB_ACTL 0x58
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#define LB_PABCDRC 0x60
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#define LB_PEFGHRC 0x64
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#define LB_WDTBA 0x84
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#define LB_BCE 0xd4
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#define LB_BC 0xd8
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#define LB_RCBA 0xf0
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#ifndef __ASSEMBLY__
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/* Root Complex Register Block */
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struct quark_rcba {
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u32 rctl;
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u32 esd;
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u32 rsvd1[3150];
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u16 rmu_ir;
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u16 d23_ir;
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u16 core_ir;
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u16 d20d21_ir;
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};
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#include <asm/io.h>
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#include <asm/pci.h>
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/**
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* qrk_pci_read_config_dword() - Read a configuration value
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*
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* @dev: PCI device address: bus, device and function
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* @offset: Dword offset within the device's configuration space
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* @valuep: Place to put the returned value
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*
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* Note: This routine is inlined to provide better performance on Quark
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*/
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static inline void qrk_pci_read_config_dword(pci_dev_t dev, int offset,
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u32 *valuep)
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{
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outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
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*valuep = inl(PCI_REG_DATA);
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}
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/**
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* qrk_pci_write_config_dword() - Write a PCI configuration value
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*
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* @dev: PCI device address: bus, device and function
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* @offset: Dword offset within the device's configuration space
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* @value: Value to write
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*
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* Note: This routine is inlined to provide better performance on Quark
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*/
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static inline void qrk_pci_write_config_dword(pci_dev_t dev, int offset,
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u32 value)
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{
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outl(dev | offset | PCI_CFG_EN, PCI_REG_ADDR);
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outl(value, PCI_REG_DATA);
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}
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/**
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* board_assert_perst() - Assert the PERST# pin
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*
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* The CPU interface to the PERST# signal on Quark is platform dependent.
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* Board-specific codes need supply this routine to assert PCIe slot reset.
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*
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* The tricky part in this routine is that any APIs that may trigger PCI
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* enumeration process are strictly forbidden, as any access to PCIe root
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* port's configuration registers will cause system hang while it is held
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* in reset.
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*/
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void board_assert_perst(void);
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/**
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* board_deassert_perst() - De-assert the PERST# pin
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*
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* The CPU interface to the PERST# signal on Quark is platform dependent.
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* Board-specific codes need supply this routine to de-assert PCIe slot reset.
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*
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* The tricky part in this routine is that any APIs that may trigger PCI
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* enumeration process are strictly forbidden, as any access to PCIe root
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* port's configuration registers will cause system hang while it is held
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* in reset.
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*/
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void board_deassert_perst(void);
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#endif /* __ASSEMBLY__ */
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#endif /* _QUARK_H_ */
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