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https://github.com/brain-hackers/u-boot-brain
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377ffcfabf
This is a workaround for 32 bit hardware limitation of TDM. T1040 has 36 bit physical addressing, TDM DMAC register are 32 bit wide but need to store address of CCSR space which lies beyond 32 bit address range. This workaround creats a LAW to enable access of TDM DMA to CCSR by mapping CCSR to overlap with DDR. A hole of 16M is created in memory using device tree. This workaround law is set only if "tdm" is defined in hwconfig. Also disable POST tests and add LIODN for TDM Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
150 lines
3.7 KiB
C
150 lines
3.7 KiB
C
/*
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* Copyright 2008-2011 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#ifndef _FSL_LAW_H_
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#define _FSL_LAW_H_
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#include <asm/io.h>
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#define LAW_EN 0x80000000
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#define SET_LAW_ENTRY(idx, a, sz, trgt) \
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{ .index = idx, .addr = a, .size = sz, .trgt_id = trgt }
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#define SET_LAW(a, sz, trgt) \
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{ .index = -1, .addr = a, .size = sz, .trgt_id = trgt }
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enum law_size {
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LAW_SIZE_4K = 0xb,
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LAW_SIZE_8K,
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LAW_SIZE_16K,
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LAW_SIZE_32K,
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LAW_SIZE_64K,
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LAW_SIZE_128K,
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LAW_SIZE_256K,
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LAW_SIZE_512K,
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LAW_SIZE_1M,
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LAW_SIZE_2M,
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LAW_SIZE_4M,
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LAW_SIZE_8M,
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LAW_SIZE_16M,
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LAW_SIZE_32M,
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LAW_SIZE_64M,
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LAW_SIZE_128M,
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LAW_SIZE_256M,
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LAW_SIZE_512M,
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LAW_SIZE_1G,
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LAW_SIZE_2G,
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LAW_SIZE_4G,
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LAW_SIZE_8G,
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LAW_SIZE_16G,
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LAW_SIZE_32G,
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};
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#define law_size_bits(sz) (__ilog2_u64(sz) - 1)
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#define lawar_size(x) (1ULL << ((x & 0x3f) + 1))
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#ifdef CONFIG_FSL_CORENET
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enum law_trgt_if {
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LAW_TRGT_IF_PCIE_1 = 0x00,
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LAW_TRGT_IF_PCIE_2 = 0x01,
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LAW_TRGT_IF_PCIE_3 = 0x02,
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LAW_TRGT_IF_PCIE_4 = 0x03,
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LAW_TRGT_IF_RIO_1 = 0x08,
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LAW_TRGT_IF_RIO_2 = 0x09,
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LAW_TRGT_IF_DDR_1 = 0x10,
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LAW_TRGT_IF_DDR_2 = 0x11, /* 2nd controller */
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LAW_TRGT_IF_DDR_3 = 0x12,
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LAW_TRGT_IF_DDR_4 = 0x13,
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LAW_TRGT_IF_DDR_INTRLV = 0x14,
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LAW_TRGT_IF_DDR_INTLV_34 = 0x15,
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LAW_TRGT_IF_DDR_INTLV_123 = 0x17,
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LAW_TRGT_IF_DDR_INTLV_1234 = 0x16,
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LAW_TRGT_IF_BMAN = 0x18,
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LAW_TRGT_IF_DCSR = 0x1d,
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LAW_TRGT_IF_CCSR = 0x1e,
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LAW_TRGT_IF_LBC = 0x1f,
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LAW_TRGT_IF_QMAN = 0x3c,
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LAW_TRGT_IF_MAPLE = 0x50,
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};
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#define LAW_TRGT_IF_DDR LAW_TRGT_IF_DDR_1
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#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
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#else
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enum law_trgt_if {
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LAW_TRGT_IF_PCI = 0x00,
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LAW_TRGT_IF_PCI_2 = 0x01,
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#ifndef CONFIG_MPC8641
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LAW_TRGT_IF_PCIE_1 = 0x02,
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#endif
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#if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132)
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LAW_TRGT_IF_OCN_DSP = 0x03,
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#else
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#if !defined(CONFIG_MPC8572) && !defined(CONFIG_P2020)
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LAW_TRGT_IF_PCIE_3 = 0x03,
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#endif
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#endif
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LAW_TRGT_IF_LBC = 0x04,
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LAW_TRGT_IF_CCSR = 0x08,
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LAW_TRGT_IF_DSP_CCSR = 0x09,
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LAW_TRGT_IF_PLATFORM_SRAM = 0x0a,
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LAW_TRGT_IF_DDR_INTRLV = 0x0b,
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LAW_TRGT_IF_RIO = 0x0c,
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#if defined(CONFIG_BSC9132)
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LAW_TRGT_IF_CLASS_DSP = 0x0d,
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#else
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LAW_TRGT_IF_RIO_2 = 0x0d,
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#endif
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LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
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LAW_TRGT_IF_DDR = 0x0f,
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LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
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/* place holder for 3-way and 4-way interleaving */
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LAW_TRGT_IF_DDR_3,
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LAW_TRGT_IF_DDR_4,
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LAW_TRGT_IF_DDR_INTLV_34,
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LAW_TRGT_IF_DDR_INTLV_123,
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LAW_TRGT_IF_DDR_INTLV_1234,
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};
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#define LAW_TRGT_IF_DDR_1 LAW_TRGT_IF_DDR
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#define LAW_TRGT_IF_PCI_1 LAW_TRGT_IF_PCI
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#define LAW_TRGT_IF_PCIX LAW_TRGT_IF_PCI
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#define LAW_TRGT_IF_PCIE_2 LAW_TRGT_IF_PCI_2
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#define LAW_TRGT_IF_RIO_1 LAW_TRGT_IF_RIO
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#define LAW_TRGT_IF_IFC LAW_TRGT_IF_LBC
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#ifdef CONFIG_MPC8641
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#define LAW_TRGT_IF_PCIE_1 LAW_TRGT_IF_PCI
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#endif
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#if defined(CONFIG_MPC8572) || defined(CONFIG_P2020)
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#define LAW_TRGT_IF_PCIE_3 LAW_TRGT_IF_PCI
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#endif
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#endif /* CONFIG_FSL_CORENET */
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struct law_entry {
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int index;
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phys_addr_t addr;
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enum law_size size;
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enum law_trgt_if trgt_id;
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};
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extern void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
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extern int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
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extern int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id);
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extern int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id);
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extern struct law_entry find_law(phys_addr_t addr);
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extern void disable_law(u8 idx);
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extern void init_laws(void);
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extern void print_laws(void);
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/* define in board code */
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extern struct law_entry law_table[];
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extern int num_law_entries;
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#endif
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