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![Vitaly Andrianov](/assets/img/avatar_default.png)
Multicore navigator consists of Network Coprocessor (NetCP) and Queue Manager sub system. More details on the hardware can be obtained from the following links:- Network Coprocessor: http://www.ti.com/lit/pdf/sprugz6 Multicore Navigator: http://www.ti.com/lit/pdf/sprugr9 Multicore navigator driver implements APIs to configure the Queue Manager and NetCP Pkt DMA. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: WingMan Kwok <w-kwok2@ti.com> Acked-by: Tom Rini <trini@ti.com>
377 lines
8.0 KiB
C
377 lines
8.0 KiB
C
/*
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* Multicore Navigator driver for TI Keystone 2 devices.
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*
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* (C) Copyright 2012-2014
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* Texas Instruments Incorporated, <www.ti.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/keystone_nav.h>
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static int soc_type =
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#ifdef CONFIG_SOC_K2HK
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k2hk;
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#endif
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struct qm_config k2hk_qm_memmap = {
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.stat_cfg = 0x02a40000,
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.queue = (struct qm_reg_queue *)0x02a80000,
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.mngr_vbusm = 0x23a80000,
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.i_lram = 0x00100000,
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.proxy = (struct qm_reg_queue *)0x02ac0000,
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.status_ram = 0x02a06000,
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.mngr_cfg = (struct qm_cfg_reg *)0x02a02000,
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.intd_cfg = 0x02a0c000,
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.desc_mem = (struct descr_mem_setup_reg *)0x02a03000,
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.region_num = 64,
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.pdsp_cmd = 0x02a20000,
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.pdsp_ctl = 0x02a0f000,
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.pdsp_iram = 0x02a10000,
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.qpool_num = 4000,
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};
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/*
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* We are going to use only one type of descriptors - host packet
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* descriptors. We staticaly allocate memory for them here
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*/
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struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
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static struct qm_config *qm_cfg;
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inline int num_of_desc_to_reg(int num_descr)
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{
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int j, num;
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for (j = 0, num = 32; j < 15; j++, num *= 2) {
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if (num_descr <= num)
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return j;
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}
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return 15;
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}
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static int _qm_init(struct qm_config *cfg)
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{
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u32 j;
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if (cfg == NULL)
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return QM_ERR;
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qm_cfg = cfg;
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qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
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qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8;
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qm_cfg->mngr_cfg->link_ram_base1 = 0;
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qm_cfg->mngr_cfg->link_ram_size1 = 0;
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qm_cfg->mngr_cfg->link_ram_base2 = 0;
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qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
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qm_cfg->desc_mem[0].start_idx = 0;
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qm_cfg->desc_mem[0].desc_reg_size =
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(((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
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num_of_desc_to_reg(HDESC_NUM);
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memset(desc_pool, 0, sizeof(desc_pool));
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for (j = 0; j < HDESC_NUM; j++)
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qm_push(&desc_pool[j], qm_cfg->qpool_num);
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return QM_OK;
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}
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int qm_init(void)
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{
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switch (soc_type) {
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case k2hk:
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return _qm_init(&k2hk_qm_memmap);
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}
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return QM_ERR;
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}
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void qm_close(void)
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{
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u32 j;
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if (qm_cfg == NULL)
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return;
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queue_close(qm_cfg->qpool_num);
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qm_cfg->mngr_cfg->link_ram_base0 = 0;
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qm_cfg->mngr_cfg->link_ram_size0 = 0;
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qm_cfg->mngr_cfg->link_ram_base1 = 0;
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qm_cfg->mngr_cfg->link_ram_size1 = 0;
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qm_cfg->mngr_cfg->link_ram_base2 = 0;
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for (j = 0; j < qm_cfg->region_num; j++) {
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qm_cfg->desc_mem[j].base_addr = 0;
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qm_cfg->desc_mem[j].start_idx = 0;
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qm_cfg->desc_mem[j].desc_reg_size = 0;
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}
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qm_cfg = NULL;
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}
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void qm_push(struct qm_host_desc *hd, u32 qnum)
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{
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u32 regd;
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if (!qm_cfg)
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return;
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cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
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regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
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writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
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}
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void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
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void *buff_ptr, u32 buff_len)
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{
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hd->orig_buff_len = buff_len;
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hd->buff_len = buff_len;
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hd->orig_buff_ptr = (u32)buff_ptr;
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hd->buff_ptr = (u32)buff_ptr;
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qm_push(hd, qnum);
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}
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struct qm_host_desc *qm_pop(u32 qnum)
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{
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u32 uhd;
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if (!qm_cfg)
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return NULL;
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uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
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if (uhd)
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cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
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return (struct qm_host_desc *)uhd;
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}
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struct qm_host_desc *qm_pop_from_free_pool(void)
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{
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if (!qm_cfg)
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return NULL;
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return qm_pop(qm_cfg->qpool_num);
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}
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void queue_close(u32 qnum)
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{
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struct qm_host_desc *hd;
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while ((hd = qm_pop(qnum)))
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;
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}
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/*
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* DMA API
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*/
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struct pktdma_cfg k2hk_netcp_pktdma = {
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.global = (struct global_ctl_regs *)0x02004000,
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.tx_ch = (struct tx_chan_regs *)0x02004400,
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.tx_ch_num = 9,
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.rx_ch = (struct rx_chan_regs *)0x02004800,
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.rx_ch_num = 26,
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.tx_sched = (u32 *)0x02004c00,
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.rx_flows = (struct rx_flow_regs *)0x02005000,
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.rx_flow_num = 32,
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.rx_free_q = 4001,
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.rx_rcv_q = 4002,
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.tx_snd_q = 648,
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};
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struct pktdma_cfg *netcp;
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static int netcp_rx_disable(void)
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{
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u32 j, v, k;
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for (j = 0; j < netcp->rx_ch_num; j++) {
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v = readl(&netcp->rx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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writel(v | CPDMA_CHAN_A_TDOWN, &netcp->rx_ch[j].cfg_a);
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for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
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udelay(100);
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v = readl(&netcp->rx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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}
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/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
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}
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/* Clear all of the flow registers */
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for (j = 0; j < netcp->rx_flow_num; j++) {
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writel(0, &netcp->rx_flows[j].control);
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writel(0, &netcp->rx_flows[j].tags);
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writel(0, &netcp->rx_flows[j].tag_sel);
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writel(0, &netcp->rx_flows[j].fdq_sel[0]);
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writel(0, &netcp->rx_flows[j].fdq_sel[1]);
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writel(0, &netcp->rx_flows[j].thresh[0]);
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writel(0, &netcp->rx_flows[j].thresh[1]);
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writel(0, &netcp->rx_flows[j].thresh[2]);
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}
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return QM_OK;
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}
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static int netcp_tx_disable(void)
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{
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u32 j, v, k;
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for (j = 0; j < netcp->tx_ch_num; j++) {
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v = readl(&netcp->tx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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writel(v | CPDMA_CHAN_A_TDOWN, &netcp->tx_ch[j].cfg_a);
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for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
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udelay(100);
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v = readl(&netcp->tx_ch[j].cfg_a);
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if (!(v & CPDMA_CHAN_A_ENABLE))
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continue;
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}
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/* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
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}
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return QM_OK;
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}
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static int _netcp_init(struct pktdma_cfg *netcp_cfg,
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struct rx_buff_desc *rx_buffers)
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{
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u32 j, v;
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struct qm_host_desc *hd;
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u8 *rx_ptr;
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if (netcp_cfg == NULL || rx_buffers == NULL ||
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rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
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return QM_ERR;
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netcp = netcp_cfg;
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netcp->rx_flow = rx_buffers->rx_flow;
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/* init rx queue */
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rx_ptr = rx_buffers->buff_ptr;
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for (j = 0; j < rx_buffers->num_buffs; j++) {
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hd = qm_pop(qm_cfg->qpool_num);
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if (hd == NULL)
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return QM_ERR;
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qm_buff_push(hd, netcp->rx_free_q,
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rx_ptr, rx_buffers->buff_len);
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rx_ptr += rx_buffers->buff_len;
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}
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netcp_rx_disable();
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/* configure rx channels */
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v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, netcp->rx_rcv_q);
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writel(v, &netcp->rx_flows[netcp->rx_flow].control);
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writel(0, &netcp->rx_flows[netcp->rx_flow].tags);
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writel(0, &netcp->rx_flows[netcp->rx_flow].tag_sel);
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v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, netcp->rx_free_q, 0,
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netcp->rx_free_q);
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writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[0]);
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writel(v, &netcp->rx_flows[netcp->rx_flow].fdq_sel[1]);
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writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[0]);
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writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[1]);
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writel(0, &netcp->rx_flows[netcp->rx_flow].thresh[2]);
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for (j = 0; j < netcp->rx_ch_num; j++)
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writel(CPDMA_CHAN_A_ENABLE, &netcp->rx_ch[j].cfg_a);
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/* configure tx channels */
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/* Disable loopback in the tx direction */
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writel(0, &netcp->global->emulation_control);
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/* TODO: make it dependend on a soc type variable */
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#ifdef CONFIG_SOC_K2HK
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/* Set QM base address, only for K2x devices */
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writel(0x23a80000, &netcp->global->qm_base_addr[0]);
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#endif
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/* Enable all channels. The current state isn't important */
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for (j = 0; j < netcp->tx_ch_num; j++) {
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writel(0, &netcp->tx_ch[j].cfg_b);
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writel(CPDMA_CHAN_A_ENABLE, &netcp->tx_ch[j].cfg_a);
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}
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return QM_OK;
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}
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int netcp_init(struct rx_buff_desc *rx_buffers)
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{
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switch (soc_type) {
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case k2hk:
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_netcp_init(&k2hk_netcp_pktdma, rx_buffers);
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return QM_OK;
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}
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return QM_ERR;
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}
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int netcp_close(void)
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{
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if (!netcp)
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return QM_ERR;
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netcp_tx_disable();
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netcp_rx_disable();
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queue_close(netcp->rx_free_q);
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queue_close(netcp->rx_rcv_q);
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queue_close(netcp->tx_snd_q);
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return QM_OK;
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}
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int netcp_send(u32 *pkt, int num_bytes, u32 swinfo2)
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{
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struct qm_host_desc *hd;
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hd = qm_pop(qm_cfg->qpool_num);
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if (hd == NULL)
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return QM_ERR;
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hd->desc_info = num_bytes;
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hd->swinfo[2] = swinfo2;
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hd->packet_info = qm_cfg->qpool_num;
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qm_buff_push(hd, netcp->tx_snd_q, pkt, num_bytes);
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return QM_OK;
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}
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void *netcp_recv(u32 **pkt, int *num_bytes)
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{
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struct qm_host_desc *hd;
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hd = qm_pop(netcp->rx_rcv_q);
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if (!hd)
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return NULL;
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*pkt = (u32 *)hd->buff_ptr;
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*num_bytes = hd->desc_info & 0x3fffff;
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return hd;
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}
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void netcp_release_rxhd(void *hd)
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{
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struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
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_hd->buff_len = _hd->orig_buff_len;
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_hd->buff_ptr = _hd->orig_buff_ptr;
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qm_push(_hd, netcp->rx_free_q);
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}
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