mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-21 10:38:00 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
129 lines
3.3 KiB
C
129 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* From coreboot src/soc/intel/broadwell/include/soc/pm.h
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*
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* Copyright (C) 2016 Google, Inc.
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*/
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#ifndef __ASM_ARCH_PM_H
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#define __ASM_ARCH_PM_H
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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#define PCIEXPWAK_STS (1 << 14)
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#define PRBTNOR_STS (1 << 11)
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#define RTC_STS (1 << 10)
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#define PWRBTN_STS (1 << 8)
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#define GBL_STS (1 << 5)
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#define BM_STS (1 << 4)
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#define TMROF_STS (1 << 0)
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#define PM1_EN 0x02
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#define PCIEXPWAK_DIS (1 << 14)
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#define RTC_EN (1 << 10)
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#define PWRBTN_EN (1 << 8)
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#define GBL_EN (1 << 5)
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#define TMROF_EN (1 << 0)
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#define PM1_CNT 0x04
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#define SLP_EN (1 << 13)
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#define SLP_TYP (7 << 10)
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#define SLP_TYP_SHIFT 10
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#define SLP_TYP_S0 0
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#define SLP_TYP_S1 1
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#define SLP_TYP_S3 5
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#define SLP_TYP_S4 6
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#define SLP_TYP_S5 7
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#define GBL_RLS (1 << 2)
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#define BM_RLD (1 << 1)
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#define SCI_EN (1 << 0)
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#define PM1_TMR 0x08
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#define SMI_EN 0x30
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#define XHCI_SMI_EN (1 << 31)
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#define ME_SMI_EN (1 << 30)
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#define GPIO_UNLOCK_SMI_EN (1 << 27)
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#define INTEL_USB2_EN (1 << 18)
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#define LEGACY_USB2_EN (1 << 17)
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#define PERIODIC_EN (1 << 14)
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#define TCO_EN (1 << 13)
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#define MCSMI_EN (1 << 11)
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#define BIOS_RLS (1 << 7)
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#define SWSMI_TMR_EN (1 << 6)
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#define APMC_EN (1 << 5)
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#define SLP_SMI_EN (1 << 4)
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#define LEGACY_USB_EN (1 << 3)
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#define BIOS_EN (1 << 2)
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#define EOS (1 << 1)
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#define GBL_SMI_EN (1 << 0)
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#define SMI_STS 0x34
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#define UPWRC 0x3c
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#define UPWRC_WS (1 << 8)
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#define UPWRC_WE (1 << 1)
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#define UPWRC_SMI (1 << 0)
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#define GPE_CNTL 0x42
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#define SWGPE_CTRL (1 << 1)
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#define DEVACT_STS 0x44
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#define PM2_CNT 0x50
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#define TCO1_CNT 0x60
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#define TCO_TMR_HLT (1 << 11)
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#define TCO1_STS 0x64
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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#define TCO2_STS_SECOND_TO (1 << 1)
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#define GPE0_REG_MAX 4
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#define GPE0_REG_SIZE 32
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#define GPE0_STS(x) (0x80 + (x * 4))
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#define GPE_31_0 0 /* 0x80/0x90 = GPE[31:0] */
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#define GPE_63_32 1 /* 0x84/0x94 = GPE[63:32] */
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#define GPE_94_64 2 /* 0x88/0x98 = GPE[94:64] */
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#define GPE_STD 3 /* 0x8c/0x9c = Standard GPE */
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#define WADT_STS (1 << 18)
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#define GP27_STS (1 << 16)
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#define PME_B0_STS (1 << 13)
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#define ME_SCI_STS (1 << 12)
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#define PME_STS (1 << 11)
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#define BATLOW_STS (1 << 10)
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#define PCI_EXP_STS (1 << 9)
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#define SMB_WAK_STS (1 << 7)
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#define TCOSCI_STS (1 << 6)
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#define SWGPE_STS (1 << 2)
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#define HOT_PLUG_STS (1 << 1)
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#define GPE0_EN(x) (0x90 + (x * 4))
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#define WADT_en (1 << 18)
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#define GP27_EN (1 << 16)
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#define PME_B0_EN (1 << 13)
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#define ME_SCI_EN (1 << 12)
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#define PME_EN (1 << 11)
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#define BATLOW_EN (1 << 10)
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#define PCI_EXP_EN (1 << 9)
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#define TCOSCI_EN (1 << 6)
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#define SWGPE_EN (1 << 2)
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#define HOT_PLUG_EN (1 << 1)
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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#define SLEEP_STATE_S0 0
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#define SLEEP_STATE_S3 3
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#define SLEEP_STATE_S5 5
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struct chipset_power_state {
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uint16_t pm1_sts;
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uint16_t pm1_en;
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uint32_t pm1_cnt;
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uint16_t tco1_sts;
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uint16_t tco2_sts;
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uint32_t gpe0_sts[4];
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uint32_t gpe0_en[4];
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uint16_t gen_pmcon1;
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uint16_t gen_pmcon2;
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uint16_t gen_pmcon3;
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int prev_sleep_state;
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uint16_t hsio_version;
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uint16_t hsio_checksum;
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};
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void power_state_get(struct udevice *pch_dev, struct chipset_power_state *ps);
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#endif
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