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https://github.com/brain-hackers/u-boot-brain
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![Peter Tyser](/assets/img/avatar_default.png)
This change lays the groundwork for the BOOTFLAG_* flags being removed. This change has the small affect of delaying 100ms on PCI initialization after a warm boot as opposed to the optimal 1ms on some boards. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> included the mpc8308_p1m board. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
167 lines
4.4 KiB
C
167 lines
4.4 KiB
C
/*
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* Copyright (C) Freescale Semiconductor, Inc. 2006-2007
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* Copyright (C) Sheldon Instruments, Inc. 2008
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*
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* Author: Ron Madrid <info@sheldoninst.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <libfdt.h>
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#include <pci.h>
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#include <mpc83xx.h>
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#include <ns16550.h>
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#include <nand.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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#ifndef CONFIG_NAND_SPL
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int checkboard(void)
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{
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puts("Board: Sheldon Instruments SIMPC8313\n");
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/*
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* Configure PCI Local Access Windows
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*/
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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/*
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* Miscellaneous late-boot configurations
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*/
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int misc_init_r(void)
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{
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int rc = 0;
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immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
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fsl_lbc_t *lbus = &immap->im_lbc;
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u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
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/* UPM Table Configuration Code */
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static uint UPMATable[] = {
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/* Read Single-Beat (RSS) */
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0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Read Burst (RBS) */
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0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c,
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0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Write Single-Beat (WSS) */
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0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Write Burst (WBS) */
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0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00,
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0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c,
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0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Refresh Timer (RTS) */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
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/* Exception Condition (EXS) */
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0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
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};
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upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
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/* Set LUPWAIT to be active low and enabled */
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out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS);
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return rc;
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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}
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#endif
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#else /* CONFIG_NAND_SPL */
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void board_init_f(ulong bootflag)
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{
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NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
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CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
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puts("NAND boot... ");
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init_timebase();
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initdram(0);
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relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC_SP, (gd_t *)gd,
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CONFIG_SYS_NAND_U_BOOT_RELOC);
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}
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void board_init_r(gd_t *gd, ulong dest_addr)
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{
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nand_boot();
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}
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void putc(char c)
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{
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if (gd->flags & GD_FLG_SILENT)
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return;
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if (c == '\n')
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
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NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
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}
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#endif
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