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![Michael Walle](/assets/img/avatar_default.png)
Add a new variable secondary_boot_code_start, which holds a pointer to the start of the spin table code. This will help to relocate the code section. While at it, move the size variable from the end to the beginning so there is a common section for the variables. Remove any other symbols. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
288 lines
7.0 KiB
C
288 lines
7.0 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2014-2015 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <image.h>
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#include <log.h>
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#include <asm/cache.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/arch/mp.h>
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#include <asm/arch/soc.h>
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#include <linux/delay.h>
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#include "cpu.h"
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#include <asm/arch-fsl-layerscape/soc.h>
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#include <efi_loader.h>
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DECLARE_GLOBAL_DATA_PTR;
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void *get_spin_tbl_addr(void)
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{
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/* the spin table is at the beginning */
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return secondary_boot_code_start;
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}
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void update_os_arch_secondary_cores(uint8_t os_arch)
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{
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u64 *table = get_spin_tbl_addr();
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int i;
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for (i = 1; i < CONFIG_MAX_CPUS; i++) {
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if (os_arch == IH_ARCH_DEFAULT)
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table[i * WORDS_PER_SPIN_TABLE_ENTRY +
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SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_SAME;
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else
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table[i * WORDS_PER_SPIN_TABLE_ENTRY +
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SPIN_TABLE_ELEM_ARCH_COMP_IDX] = OS_ARCH_DIFF;
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}
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}
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#ifdef CONFIG_FSL_LSCH3
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static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
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u32 mpidr = 0;
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mpidr = ((cluster << 8) | core);
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/*
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* mpidr_el1 register value of core which needs to be released
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* is written to scratchrw[6] register
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*/
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gur_out32(&gur->scratchrw[6], mpidr);
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asm volatile("dsb st" : : : "memory");
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rst->brrl |= 1 << ((cluster * cluster_cores) + core);
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asm volatile("dsb st" : : : "memory");
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/*
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* scratchrw[6] register value is polled
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* when the value becomes zero, this means that this core is up
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* and running, next core can be released now
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*/
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while (gur_in32(&gur->scratchrw[6]) != 0)
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;
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}
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#endif
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int fsl_layerscape_wake_seconday_cores(void)
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{
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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#ifdef CONFIG_FSL_LSCH3
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struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR);
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u32 svr, ver, cluster, type;
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int j = 0, cluster_cores = 0;
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#elif defined(CONFIG_FSL_LSCH2)
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struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR);
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#endif
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u32 cores, cpu_up_mask = 1;
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int i, timeout = 10;
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u64 *table;
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#ifdef COUNTER_FREQUENCY_REAL
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/* update for secondary cores */
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__real_cntfrq = COUNTER_FREQUENCY_REAL;
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flush_dcache_range((unsigned long)&__real_cntfrq,
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(unsigned long)&__real_cntfrq + 8);
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#endif
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cores = cpu_mask();
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/* Clear spin table so that secondary processors
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* observe the correct value after waking up from wfe.
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*/
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table = get_spin_tbl_addr();
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memset(table, 0, CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE);
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flush_dcache_range((unsigned long)table,
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(unsigned long)table +
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(CONFIG_MAX_CPUS*SPIN_TABLE_ELEM_SIZE));
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debug("Waking secondary cores to start from %lx\n", gd->relocaddr);
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#ifdef CONFIG_FSL_LSCH3
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gur_out32(&gur->bootlocptrh, (u32)(gd->relocaddr >> 32));
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gur_out32(&gur->bootlocptrl, (u32)gd->relocaddr);
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svr = gur_in32(&gur->svr);
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ver = SVR_SOC_VER(svr);
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if (ver == SVR_LS2080A || ver == SVR_LS2085A) {
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gur_out32(&gur->scratchrw[6], 1);
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asm volatile("dsb st" : : : "memory");
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rst->brrl = cores;
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asm volatile("dsb st" : : : "memory");
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} else {
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/*
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* Release the cores out of reset one-at-a-time to avoid
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* power spikes
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*/
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i = 0;
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cluster = in_le32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type &&
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TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
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cluster_cores++;
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}
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do {
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cluster = in_le32(&gur->tp_cluster[i].lower);
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for (j = 0; j < TP_INIT_PER_CLUSTER; j++) {
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type = initiator_type(cluster, j);
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if (type &&
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TP_ITYP_TYPE(type) == TP_ITYP_TYPE_ARM)
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wake_secondary_core_n(i, j,
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cluster_cores);
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}
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i++;
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} while ((cluster & TP_CLUSTER_EOC) != TP_CLUSTER_EOC);
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}
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#elif defined(CONFIG_FSL_LSCH2)
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scfg_out32(&scfg->scratchrw[0], (u32)(gd->relocaddr >> 32));
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scfg_out32(&scfg->scratchrw[1], (u32)gd->relocaddr);
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asm volatile("dsb st" : : : "memory");
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gur_out32(&gur->brrl, cores);
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asm volatile("dsb st" : : : "memory");
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/* Bootup online cores */
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scfg_out32(&scfg->corebcr, cores);
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#endif
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/* This is needed as a precautionary measure.
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* If some code before this has accidentally released the secondary
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* cores then the pre-bootloader code will trap them in a "wfe" unless
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* the scratchrw[6] is set. In this case we need a sev here to get these
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* cores moving again.
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*/
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asm volatile("sev");
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while (timeout--) {
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flush_dcache_range((unsigned long)table, (unsigned long)table +
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CONFIG_MAX_CPUS * 64);
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for (i = 1; i < CONFIG_MAX_CPUS; i++) {
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if (table[i * WORDS_PER_SPIN_TABLE_ENTRY +
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SPIN_TABLE_ELEM_STATUS_IDX])
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cpu_up_mask |= 1 << i;
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}
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if (hweight32(cpu_up_mask) == hweight32(cores))
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break;
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udelay(10);
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}
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if (timeout <= 0) {
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printf("CPU: Failed to bring up some cores (mask 0x%x)\n",
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cores ^ cpu_up_mask);
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return 1;
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}
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printf("CPU: %d cores online\n", hweight32(cores));
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return 0;
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}
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int is_core_valid(unsigned int core)
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{
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return !!((1 << core) & cpu_mask());
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}
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static int is_pos_valid(unsigned int pos)
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{
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return !!((1 << pos) & cpu_pos_mask());
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}
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int is_core_online(u64 cpu_id)
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{
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u64 *table = get_spin_tbl_addr();
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int pos = id_to_core(cpu_id);
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table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
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return table[SPIN_TABLE_ELEM_STATUS_IDX] == 1;
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}
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int cpu_reset(u32 nr)
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{
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puts("Feature is not implemented.\n");
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return 0;
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}
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int cpu_disable(u32 nr)
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{
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puts("Feature is not implemented.\n");
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return 0;
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}
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static int core_to_pos(int nr)
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{
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u32 cores = cpu_pos_mask();
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int i, count = 0;
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if (nr == 0) {
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return 0;
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} else if (nr >= hweight32(cores)) {
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puts("Not a valid core number.\n");
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return -1;
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}
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for (i = 1; i < 32; i++) {
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if (is_pos_valid(i)) {
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count++;
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if (count == nr)
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break;
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}
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}
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if (count != nr)
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return -1;
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return i;
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}
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int cpu_status(u32 nr)
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{
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u64 *table = get_spin_tbl_addr();
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int pos;
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if (nr == 0) {
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printf("table base @ 0x%p\n", table);
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} else {
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pos = core_to_pos(nr);
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if (pos < 0)
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return -1;
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table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
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printf("table @ 0x%p\n", table);
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printf(" addr - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX]);
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printf(" status - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_STATUS_IDX]);
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printf(" lpid - 0x%016llx\n",
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table[SPIN_TABLE_ELEM_LPID_IDX]);
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}
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return 0;
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}
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int cpu_release(u32 nr, int argc, char *const argv[])
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{
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u64 boot_addr;
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u64 *table = get_spin_tbl_addr();
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int pos;
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pos = core_to_pos(nr);
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if (pos <= 0)
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return -1;
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table += pos * WORDS_PER_SPIN_TABLE_ENTRY;
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boot_addr = simple_strtoull(argv[0], NULL, 16);
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table[SPIN_TABLE_ELEM_ENTRY_ADDR_IDX] = boot_addr;
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flush_dcache_range((unsigned long)table,
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(unsigned long)table + SPIN_TABLE_ELEM_SIZE);
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asm volatile("dsb st");
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/*
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* The secondary CPUs polling the spin-table above for a non-zero
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* value. To save power "wfe" is called. Thus call "sev" here to
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* wake the CPUs and let them check the spin-table again (see
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* slave_cpu loop in lowlevel.S)
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*/
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asm volatile("sev");
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return 0;
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}
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