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![Magnus Lilja](/assets/img/avatar_default.png)
Commit f9b6a1575d
, "i.MX31: fix SPI
driver for shorter than 32 bit" broke 32 bit transfers. This patch
makes single 32 bit transfer work again.
Transfer lengths that are known not to work will abort and print
an error message.
Tested on i.MX31 Litekit and i.MX31 PDK using 32 bit transfers to
the MC13783/ATLAS chip (using the 'date' command).
Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
259 lines
6.3 KiB
C
259 lines
6.3 KiB
C
/*
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* Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*
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*/
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#include <common.h>
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#include <malloc.h>
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#include <spi.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#ifdef CONFIG_MX27
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/* i.MX27 has a completely wrong register layout and register definitions in the
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* datasheet, the correct one is in the Freescale's Linux driver */
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#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \
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"See linux mxc_spi driver from Freescale for details."
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#else
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#include <asm/arch/mx31.h>
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#define MXC_CSPIRXDATA 0x00
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#define MXC_CSPITXDATA 0x04
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#define MXC_CSPICTRL 0x08
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#define MXC_CSPIINT 0x0C
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#define MXC_CSPIDMA 0x10
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#define MXC_CSPISTAT 0x14
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#define MXC_CSPIPERIOD 0x18
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#define MXC_CSPITEST 0x1C
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#define MXC_CSPIRESET 0x00
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#define MXC_CSPICTRL_EN (1 << 0)
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#define MXC_CSPICTRL_MODE (1 << 1)
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#define MXC_CSPICTRL_XCH (1 << 2)
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#define MXC_CSPICTRL_SMC (1 << 3)
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#define MXC_CSPICTRL_POL (1 << 4)
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#define MXC_CSPICTRL_PHA (1 << 5)
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#define MXC_CSPICTRL_SSCTL (1 << 6)
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#define MXC_CSPICTRL_SSPOL (1 << 7)
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#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24)
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#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8)
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#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16)
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#define MXC_CSPIPERIOD_32KHZ (1 << 15)
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static unsigned long spi_bases[] = {
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0x43fa4000,
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0x50010000,
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0x53f84000,
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};
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#endif
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struct mxc_spi_slave {
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struct spi_slave slave;
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unsigned long base;
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u32 ctrl_reg;
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int gpio;
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};
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static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave)
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{
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return container_of(slave, struct mxc_spi_slave, slave);
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}
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static inline u32 reg_read(unsigned long addr)
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{
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return *(volatile unsigned long*)addr;
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}
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static inline void reg_write(unsigned long addr, u32 val)
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{
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*(volatile unsigned long*)addr = val;
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}
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static u32 spi_xchg_single(struct spi_slave *slave, u32 data, int bitlen,
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unsigned long flags)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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unsigned int cfg_reg = reg_read(mxcs->base + MXC_CSPICTRL);
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mxcs->ctrl_reg = (mxcs->ctrl_reg & ~MXC_CSPICTRL_BITCOUNT(31)) |
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MXC_CSPICTRL_BITCOUNT(bitlen - 1);
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if (cfg_reg != mxcs->ctrl_reg)
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
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if (mxcs->gpio > 0 && (flags & SPI_XFER_BEGIN))
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mx31_gpio_set(mxcs->gpio, mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL);
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reg_write(mxcs->base + MXC_CSPITXDATA, data);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg | MXC_CSPICTRL_XCH);
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while (reg_read(mxcs->base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH)
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;
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if (mxcs->gpio > 0 && (flags & SPI_XFER_END)) {
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mx31_gpio_set(mxcs->gpio,
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!(mxcs->ctrl_reg & MXC_CSPICTRL_SSPOL));
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}
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return reg_read(mxcs->base + MXC_CSPIRXDATA);
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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void *din, unsigned long flags)
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{
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int n_blks = (bitlen + 31) / 32;
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u32 *out_l, *in_l;
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int i;
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if ((int)dout & 3 || (int)din & 3) {
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printf("Error: unaligned buffers in: %p, out: %p\n", din, dout);
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return 1;
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}
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/* This driver is currently partly broken, alert the user */
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if (bitlen > 16 && (bitlen % 32)) {
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printf("Error: SPI transfer with bitlen=%d is broken.\n",
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bitlen);
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return 1;
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}
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for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout;
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i < n_blks;
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i++, in_l++, out_l++, bitlen -= 32) {
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u32 data = spi_xchg_single(slave, *out_l, bitlen, flags);
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/* Check if we're only transfering 8 or 16 bits */
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if (!i) {
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if (bitlen < 9)
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*(u8 *)din = data;
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else if (bitlen < 17)
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*(u16 *)din = data;
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else
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*in_l = data;
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}
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}
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return 0;
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}
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void spi_init(void)
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{
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}
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static int decode_cs(struct mxc_spi_slave *mxcs, unsigned int cs)
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{
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int ret;
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/*
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* Some SPI devices require active chip-select over multiple
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* transactions, we achieve this using a GPIO. Still, the SPI
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* controller has to be configured to use one of its own chipselects.
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* To use this feature you have to call spi_setup_slave() with
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* cs = internal_cs | (gpio << 8), and you have to use some unused
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* on this SPI controller cs between 0 and 3.
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*/
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if (cs > 3) {
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mxcs->gpio = cs >> 8;
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cs &= 3;
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ret = mx31_gpio_direction(mxcs->gpio, MX31_GPIO_DIRECTION_OUT);
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if (ret) {
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printf("mxc_spi: cannot setup gpio %d\n", mxcs->gpio);
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return -EINVAL;
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}
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} else {
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mxcs->gpio = -1;
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}
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return cs;
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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unsigned int ctrl_reg;
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struct mxc_spi_slave *mxcs;
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int ret;
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if (bus >= ARRAY_SIZE(spi_bases))
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return NULL;
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mxcs = malloc(sizeof(struct mxc_spi_slave));
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if (!mxcs)
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return NULL;
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ret = decode_cs(mxcs, cs);
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if (ret < 0) {
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free(mxcs);
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return NULL;
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}
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cs = ret;
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ctrl_reg = MXC_CSPICTRL_CHIPSELECT(cs) |
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MXC_CSPICTRL_BITCOUNT(31) |
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MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */
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MXC_CSPICTRL_EN |
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MXC_CSPICTRL_MODE;
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if (mode & SPI_CPHA)
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ctrl_reg |= MXC_CSPICTRL_PHA;
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if (!(mode & SPI_CPOL))
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ctrl_reg |= MXC_CSPICTRL_POL;
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if (mode & SPI_CS_HIGH)
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ctrl_reg |= MXC_CSPICTRL_SSPOL;
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mxcs->slave.bus = bus;
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mxcs->slave.cs = cs;
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mxcs->base = spi_bases[bus];
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mxcs->ctrl_reg = ctrl_reg;
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return &mxcs->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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free(mxcs);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave);
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reg_write(mxcs->base + MXC_CSPIRESET, 1);
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udelay(1);
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reg_write(mxcs->base + MXC_CSPICTRL, mxcs->ctrl_reg);
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reg_write(mxcs->base + MXC_CSPIPERIOD,
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MXC_CSPIPERIOD_32KHZ);
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reg_write(mxcs->base + MXC_CSPIINT, 0);
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return 0;
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}
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void spi_release_bus(struct spi_slave *slave)
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{
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/* TODO: Shut the controller down */
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}
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