mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-17 15:38:51 +09:00
![Stefan Roese](/assets/img/avatar_default.png)
This patch removes the duplicted implementations of the pci_master_init() function by introducing a weak default function for it. It can be overridden by a board specific version. Signed-off-by: Stefan Roese <sr@denx.de>
433 lines
11 KiB
C
433 lines
11 KiB
C
/*
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* (C) Copyright 2007
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* Stefan Roese, DENX Software Engineering, sr@denx.de.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <ppc440.h>
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#include <asm/processor.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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DECLARE_GLOBAL_DATA_PTR;
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extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
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ulong flash_get_size(ulong base, int banknum);
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int misc_init_r_kbd(void);
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int board_early_init_f(void)
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{
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u32 sdr0_pfc1, sdr0_pfc2;
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u32 reg;
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/* PLB Write pipelining disabled. Denali Core workaround */
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mtdcr(PLB0_ACR, 0xDE000000);
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mtdcr(PLB1_ACR, 0xDE000000);
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/*--------------------------------------------------------------------
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* Setup the interrupt controller polarities, triggers, etc.
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*-------------------------------------------------------------------*/
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mtdcr(UIC0SR, 0xffffffff); /* clear all. if write with 1 then the status is cleared */
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mtdcr(UIC0ER, 0x00000000); /* disable all */
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mtdcr(UIC0CR, 0x00000000); /* we have not critical interrupts at the moment */
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mtdcr(UIC0PR, 0xFFBFF1EF); /* Adjustment of the polarity */
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mtdcr(UIC0TR, 0x00000900); /* per ref-board manual */
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mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC0SR, 0xffffffff); /* clear all */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC1ER, 0x00000000); /* disable all */
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mtdcr(UIC1CR, 0x00000000); /* all non-critical */
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mtdcr(UIC1PR, 0xFFFFC6A5); /* Adjustment of the polarity */
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mtdcr(UIC1TR, 0x60000040); /* per ref-board manual */
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mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC1SR, 0xffffffff); /* clear all */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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mtdcr(UIC2ER, 0x00000000); /* disable all */
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mtdcr(UIC2CR, 0x00000000); /* all non-critical */
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mtdcr(UIC2PR, 0x27C00000); /* Adjustment of the polarity */
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mtdcr(UIC2TR, 0x3C000000); /* per ref-board manual */
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mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 is within DDRAM */
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mtdcr(UIC2SR, 0xffffffff); /* clear all */
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/* Trace Pins are disabled. SDR0_PFC0 Register */
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mtsdr(SDR0_PFC0, 0x0);
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/* select Ethernet pins */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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/* SMII via ZMII */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
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SDR0_PFC1_SELECT_CONFIG_6;
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mfsdr(SDR0_PFC2, sdr0_pfc2);
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sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
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SDR0_PFC2_SELECT_CONFIG_6;
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/* enable SPI (SCP) */
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sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_SCP_SEL;
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mtsdr(SDR0_PFC2, sdr0_pfc2);
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_PFC4, 0x80000000);
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/* PCI arbiter disabled */
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/* PCI Host Configuration disbaled */
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mfsdr(SDR0_PCI0, reg);
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reg = 0;
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mtsdr(SDR0_PCI0, 0x00000000 | reg);
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gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
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#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
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gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
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reg = 0; /* reuse as counter */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
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& ~CONFIG_SYS_DSPIC_TEST_MASK);
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while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
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udelay(1000);
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}
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gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
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if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
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/* set "boot error" flag */
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out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
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in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
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CONFIG_SYS_DSPIC_TEST_MASK);
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}
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#endif
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/*
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* Reset PHY's:
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* The PHY's need a 2nd reset pulse, since the MDIO address is latched
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* upon reset, and with the first reset upon powerup, the addresses are
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* not latched reliable, since the IRQ line is multiplexed with an
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* MDIO address. A 2nd reset at this time will make sure, that the
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* correct address is latched.
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*/
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
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udelay(1000);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
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udelay(1000);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
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gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
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return 0;
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}
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/*---------------------------------------------------------------------------+
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| misc_init_r.
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+---------------------------------------------------------------------------*/
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int misc_init_r(void)
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{
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u32 pbcr;
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int size_val = 0;
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u32 reg;
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unsigned long usb2d0cr = 0;
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unsigned long usb2phy0cr, usb2h0cr = 0;
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unsigned long sdr0_pfc1;
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/*
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* FLASH stuff...
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*/
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/* Re-do sizing to get full correct info */
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/* adjust flash start and offset */
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gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
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gd->bd->bi_flashoffset = 0;
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mfebc(PB0CR, pbcr);
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switch (gd->bd->bi_flashsize) {
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case 1 << 20:
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size_val = 0;
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break;
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case 2 << 20:
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size_val = 1;
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break;
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case 4 << 20:
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size_val = 2;
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break;
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case 8 << 20:
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size_val = 3;
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break;
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case 16 << 20:
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size_val = 4;
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break;
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case 32 << 20:
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size_val = 5;
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break;
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case 64 << 20:
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size_val = 6;
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break;
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case 128 << 20:
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size_val = 7;
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break;
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}
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pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
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mtebc(PB0CR, pbcr);
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/*
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* Re-check to get correct base address
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*/
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flash_get_size(gd->bd->bi_flashstart, 0);
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/* Monitor protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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-CONFIG_SYS_MONITOR_LEN,
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0xffffffff,
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&flash_info[1]);
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/* Env protection ON by default */
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(void)flash_protect(FLAG_PROTECT_SET,
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CONFIG_ENV_ADDR_REDUND,
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CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
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&flash_info[1]);
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/*
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* USB suff...
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*/
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/* SDR Setting */
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mfsdr(SDR0_PFC1, sdr0_pfc1);
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mfsdr(SDR0_USB0, usb2d0cr);
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mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mfsdr(SDR0_USB2H0CR, usb2h0cr);
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS; /*0*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST; /*1*/
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usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
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usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST; /*1*/
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/* An 8-bit/60MHz interface is the only possible alternative
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when connecting the Device to the PHY */
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usb2h0cr = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
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usb2h0cr = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ; /*1*/
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mtsdr(SDR0_PFC1, sdr0_pfc1);
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mtsdr(SDR0_USB0, usb2d0cr);
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mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
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mtsdr(SDR0_USB2H0CR, usb2h0cr);
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/*
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* Clear resets
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*/
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udelay (1000);
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mtsdr(SDR0_SRST1, 0x00000000);
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udelay (1000);
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mtsdr(SDR0_SRST0, 0x00000000);
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printf("USB: Host(int phy) Device(ext phy)\n");
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/*
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* Clear PLB4A0_ACR[WRP]
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* This fix will make the MAL burst disabling patch for the Linux
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* EMAC driver obsolete.
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*/
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reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP;
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mtdcr(PLB4_ACR, reg);
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/*
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* Init matrix keyboard
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*/
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misc_init_r_kbd();
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return 0;
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}
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int checkboard(void)
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{
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char *s = getenv("serial#");
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printf("Board: lwmon5");
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if (s != NULL) {
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puts(", serial# ");
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puts(s);
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}
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putc('\n');
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return (0);
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}
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void hw_watchdog_reset(void)
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{
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int val;
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#if defined(CONFIG_WD_MAX_RATE)
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unsigned long long ct = get_ticks();
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/*
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* Don't allow watch-dog triggering more frequently than
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* the predefined value CONFIG_WD_MAX_RATE [ticks].
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*/
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if (ct >= gd->wdt_last) {
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if ((ct - gd->wdt_last) < CONFIG_WD_MAX_RATE)
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return;
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} else {
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/* Time base counter had been reset */
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if (((unsigned long long)(-1) - gd->wdt_last + ct) <
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CONFIG_WD_MAX_RATE)
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return;
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}
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gd->wdt_last = get_ticks();
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#endif
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/*
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* Toggle watchdog output
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*/
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val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
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gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
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}
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int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
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{
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if (argc < 2) {
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cmd_usage(cmdtp);
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return 1;
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}
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if ((strcmp(argv[1], "on") == 0)) {
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gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
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} else if ((strcmp(argv[1], "off") == 0)) {
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gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
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} else {
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cmd_usage(cmdtp);
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return 1;
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}
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return 0;
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}
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U_BOOT_CMD(
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eepromwp, 2, 0, do_eeprom_wp,
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"eeprom write protect off/on",
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"<on|off> - enable (on) or disable (off) I2C EEPROM write protect"
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);
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#if defined(CONFIG_VIDEO)
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#include <video_fb.h>
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#include <mb862xx.h>
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extern GraphicDevice mb862xx;
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static const gdc_regs init_regs [] =
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{
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{0x0100, 0x00000f00},
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{0x0020, 0x801401df},
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{0x0024, 0x00000000},
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{0x0028, 0x00000000},
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{0x002c, 0x00000000},
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{0x0110, 0x00000000},
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{0x0114, 0x00000000},
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{0x0118, 0x01df0280},
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{0x0004, 0x031f0000},
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{0x0008, 0x027f027f},
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{0x000c, 0x015f028f},
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{0x0010, 0x020c0000},
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{0x0014, 0x01df01ea},
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{0x0018, 0x00000000},
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{0x001c, 0x01e00280},
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{0x0100, 0x80010f00},
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{0x0, 0x0}
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};
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const gdc_regs *board_get_regs (void)
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{
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return init_regs;
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}
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/* Returns Lime base address */
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unsigned int board_video_init (void)
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{
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/*
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* Reset Lime controller
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*/
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gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
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udelay(500);
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gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
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mb862xx.winSizeX = 640;
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mb862xx.winSizeY = 480;
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mb862xx.gdfBytesPP = 2;
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mb862xx.gdfIndex = GDF_15BIT_555RGB;
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return CONFIG_SYS_LIME_BASE_0;
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}
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#define DEFAULT_BRIGHTNESS 0x64
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static void board_backlight_brightness(int brightness)
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{
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if (brightness > 0) {
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/* pwm duty, lamp on */
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
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} else {
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/* lamp off */
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
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out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
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}
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}
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void board_backlight_switch (int flag)
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{
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char * param;
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int rc;
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if (flag) {
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param = getenv("brightness");
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rc = param ? simple_strtol(param, NULL, 10) : -1;
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if (rc < 0)
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rc = DEFAULT_BRIGHTNESS;
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} else {
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rc = 0;
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}
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board_backlight_brightness(rc);
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}
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#if defined(CONFIG_CONSOLE_EXTRA_INFO)
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/*
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* Return text to be printed besides the logo.
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*/
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void video_get_info_str (int line_number, char *info)
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{
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if (line_number == 1) {
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strcpy (info, " Board: Lwmon5 (Liebherr Elektronik GmbH)");
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} else {
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info [0] = '\0';
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}
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}
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#endif
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#endif /* CONFIG_VIDEO */
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void board_reset(void)
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{
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gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
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}
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