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![]() - Move the TLB entry of PIXIS_BASE from TLB0 to TLB1[8], because in CAMP mode, all the TLB0 entries will be invalidated after cpu1 brings up kernel, thus cpu0 can not access PIXIS_BASE anymore (any access will cause DataTLBError exception) - Set CONFIG_SYS_DDR_TLB_START to 9 for MPC8572DS board. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> |
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.. | ||
config.mk | ||
ddr.c | ||
law.c | ||
Makefile | ||
mpc8572ds.c | ||
tlb.c | ||
u-boot.lds |