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![Lars Povlsen](/assets/img/avatar_default.png)
This add device tree binding documentation for the MSCC serial GPIO driver. Signed-off-by: Lars Povlsen <lars.povlsen@microsemi.com> Acked-by: Linus Walleij <linus.walleij@linaro.org>
46 lines
1.7 KiB
Plaintext
46 lines
1.7 KiB
Plaintext
Microsemi Corporation (MSCC) Serial GPIO driver
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The MSCC serial GPIO extends the number or GPIO's on the system by
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means of 4 dedicated pins: one input, one output, one clock and one
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strobe pin. By attaching a number of (external) shift registers, the
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effective GPIO count can be extended by up to 128 GPIO's per
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controller.
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Required properties:
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- compatible : "mscc,luton-sgpio" or "mscc,ocelot-sgpio"
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- clock: Reference clock used to generate clock divider setting. See
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mscc,sgpio-frequency property.
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- reg : Physical base address and length of the controller's registers.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters:
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- bit 0 specifies polarity (0 for normal, 1 for inverted)
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- gpio-controller : Marks the device node as a GPIO controller.
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- gpio-ranges: Standard gpio range(s): phandle, gpio base, pinctrl base
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and count.
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Optional properties:
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- ngpios: See gpio.txt
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- mscc,sgpio-frequency: The frequency at which the serial bitstream is
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generated and sampled. Default: 12500000 (Hz).
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- mscc,sgpio-ports: A bitmask (32 bits) of which ports are enabled in
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the serialized gpio stream. One 'port' will transport from 1 to 4
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gpio bits. Default: 0xFFFFFFFF.
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Typically the pinctrl-0 and pinctrl-names properties will also be
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present to enable the use of the SIO CLK, LD, DI and DO for some
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regular GPIO pins.
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Example:
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sgpio: gpio@10700f8 {
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compatible = "mscc,ocelot-sgpio";
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pinctrl-0 = <&sgpio_pins>;
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pinctrl-names = "default";
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reg = <0x10700f8 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&sgpio 0 0 64>;
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mscc,sgpio-frequency = <12500>;
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mscc,sgpio-ports = <0x000FFFFF>;
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};
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