mirror of
https://github.com/brain-hackers/u-boot-brain
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306fa01279
After wakeup from deep sleep, Clear EPU registers as early as possible to prevent from possible issue. It's also safe to clear at normal boot. Signed-off-by: Chenhui Zhao <chenhui.zhao@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
120 lines
2.3 KiB
C
120 lines
2.3 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/clock.h>
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#include <asm/io.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <fsl_esdhc.h>
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#include "fsl_epu.h"
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DECLARE_GLOBAL_DATA_PTR;
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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char buf1[32], buf2[32];
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struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
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unsigned int svr, major, minor, ver, i;
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svr = in_be32(&gur->svr);
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major = SVR_MAJ(svr);
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minor = SVR_MIN(svr);
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puts("CPU: Freescale LayerScape ");
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ver = SVR_SOC_VER(svr);
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switch (ver) {
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case SOC_VER_SLS1020:
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puts("SLS1020");
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break;
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case SOC_VER_LS1020:
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puts("LS1020");
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break;
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case SOC_VER_LS1021:
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puts("LS1021");
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break;
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case SOC_VER_LS1022:
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puts("LS1022");
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break;
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default:
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puts("Unknown");
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break;
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}
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if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
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puts("E");
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printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
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puts("Clock Configuration:");
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printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
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printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
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printf("DDR:%-4s MHz (%s MT/s data rate), ",
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strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
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puts("\n");
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/* Display the RCW, so that no one gets confused as to what RCW
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* we're actually using for this boot.
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*/
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puts("Reset Configuration Word (RCW):");
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for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
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u32 rcw = in_be32(&gur->rcwsr[i]);
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if ((i % 4) == 0)
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printf("\n %08x:", i * 4);
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printf(" %08x", rcw);
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}
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puts("\n");
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return 0;
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}
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#endif
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void enable_caches(void)
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{
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#ifndef CONFIG_SYS_ICACHE_OFF
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icache_enable();
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#endif
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#ifndef CONFIG_SYS_DCACHE_OFF
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dcache_enable();
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#endif
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}
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#ifdef CONFIG_FSL_ESDHC
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int cpu_mmc_init(bd_t *bis)
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{
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return fsl_esdhc_mmc_init(bis);
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}
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#endif
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int cpu_eth_init(bd_t *bis)
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{
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#ifdef CONFIG_TSEC_ENET
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tsec_standard_init(bis);
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#endif
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return 0;
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}
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int arch_cpu_init(void)
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{
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void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
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/*
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* After wakeup from deep sleep, Clear EPU registers
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* as early as possible to prevent from possible issue.
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* It's also safe to clear at normal boot.
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*/
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fsl_epu_clean(epu_base);
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return 0;
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}
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