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![Simon Glass](/assets/img/avatar_default.png)
This converts the Tegra SPI drivers to use driver model. This is tested on: - Tegra20 - trimslice - Tegra30 - beaver - Tegra124 - dalmore (not tested on Tegra124) Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
413 lines
12 KiB
C
413 lines
12 KiB
C
/*
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* NVIDIA Tegra SPI controller (T114 and later)
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*
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* Copyright (c) 2010-2013 NVIDIA Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch-tegra/clk_rst.h>
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#include <spi.h>
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#include <fdtdec.h>
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#include "tegra_spi.h"
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DECLARE_GLOBAL_DATA_PTR;
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/* COMMAND1 */
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#define SPI_CMD1_GO (1 << 31)
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#define SPI_CMD1_M_S (1 << 30)
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#define SPI_CMD1_MODE_MASK 0x3
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#define SPI_CMD1_MODE_SHIFT 28
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#define SPI_CMD1_CS_SEL_MASK 0x3
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#define SPI_CMD1_CS_SEL_SHIFT 26
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#define SPI_CMD1_CS_POL_INACTIVE3 (1 << 25)
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#define SPI_CMD1_CS_POL_INACTIVE2 (1 << 24)
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#define SPI_CMD1_CS_POL_INACTIVE1 (1 << 23)
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#define SPI_CMD1_CS_POL_INACTIVE0 (1 << 22)
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#define SPI_CMD1_CS_SW_HW (1 << 21)
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#define SPI_CMD1_CS_SW_VAL (1 << 20)
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#define SPI_CMD1_IDLE_SDA_MASK 0x3
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#define SPI_CMD1_IDLE_SDA_SHIFT 18
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#define SPI_CMD1_BIDIR (1 << 17)
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#define SPI_CMD1_LSBI_FE (1 << 16)
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#define SPI_CMD1_LSBY_FE (1 << 15)
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#define SPI_CMD1_BOTH_EN_BIT (1 << 14)
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#define SPI_CMD1_BOTH_EN_BYTE (1 << 13)
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#define SPI_CMD1_RX_EN (1 << 12)
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#define SPI_CMD1_TX_EN (1 << 11)
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#define SPI_CMD1_PACKED (1 << 5)
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#define SPI_CMD1_BIT_LEN_MASK 0x1F
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#define SPI_CMD1_BIT_LEN_SHIFT 0
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/* COMMAND2 */
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#define SPI_CMD2_TX_CLK_TAP_DELAY (1 << 6)
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#define SPI_CMD2_TX_CLK_TAP_DELAY_MASK (0x3F << 6)
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#define SPI_CMD2_RX_CLK_TAP_DELAY (1 << 0)
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#define SPI_CMD2_RX_CLK_TAP_DELAY_MASK (0x3F << 0)
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/* TRANSFER STATUS */
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#define SPI_XFER_STS_RDY (1 << 30)
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/* FIFO STATUS */
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#define SPI_FIFO_STS_CS_INACTIVE (1 << 31)
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#define SPI_FIFO_STS_FRAME_END (1 << 30)
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#define SPI_FIFO_STS_RX_FIFO_FLUSH (1 << 15)
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#define SPI_FIFO_STS_TX_FIFO_FLUSH (1 << 14)
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#define SPI_FIFO_STS_ERR (1 << 8)
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#define SPI_FIFO_STS_TX_FIFO_OVF (1 << 7)
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#define SPI_FIFO_STS_TX_FIFO_UNR (1 << 6)
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#define SPI_FIFO_STS_RX_FIFO_OVF (1 << 5)
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#define SPI_FIFO_STS_RX_FIFO_UNR (1 << 4)
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#define SPI_FIFO_STS_TX_FIFO_FULL (1 << 3)
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#define SPI_FIFO_STS_TX_FIFO_EMPTY (1 << 2)
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#define SPI_FIFO_STS_RX_FIFO_FULL (1 << 1)
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#define SPI_FIFO_STS_RX_FIFO_EMPTY (1 << 0)
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#define SPI_TIMEOUT 1000
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#define TEGRA_SPI_MAX_FREQ 52000000
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struct spi_regs {
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u32 command1; /* 000:SPI_COMMAND1 register */
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u32 command2; /* 004:SPI_COMMAND2 register */
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u32 timing1; /* 008:SPI_CS_TIM1 register */
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u32 timing2; /* 00c:SPI_CS_TIM2 register */
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u32 xfer_status;/* 010:SPI_TRANS_STATUS register */
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u32 fifo_status;/* 014:SPI_FIFO_STATUS register */
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u32 tx_data; /* 018:SPI_TX_DATA register */
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u32 rx_data; /* 01c:SPI_RX_DATA register */
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u32 dma_ctl; /* 020:SPI_DMA_CTL register */
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u32 dma_blk; /* 024:SPI_DMA_BLK register */
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u32 rsvd[56]; /* 028-107 reserved */
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u32 tx_fifo; /* 108:SPI_FIFO1 register */
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u32 rsvd2[31]; /* 10c-187 reserved */
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u32 rx_fifo; /* 188:SPI_FIFO2 register */
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u32 spare_ctl; /* 18c:SPI_SPARE_CTRL register */
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};
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struct tegra114_spi_priv {
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struct spi_regs *regs;
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unsigned int freq;
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unsigned int mode;
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int periph_id;
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int valid;
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int last_transaction_us;
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};
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static int tegra114_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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const void *blob = gd->fdt_blob;
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int node = bus->of_offset;
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plat->base = fdtdec_get_addr(blob, node, "reg");
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plat->periph_id = clock_decode_periph_id(blob, node);
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if (plat->periph_id == PERIPH_ID_NONE) {
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debug("%s: could not decode periph id %d\n", __func__,
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plat->periph_id);
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return -FDT_ERR_NOTFOUND;
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}
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/* Use 500KHz as a suitable default */
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plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
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500000);
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plat->deactivate_delay_us = fdtdec_get_int(blob, node,
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"spi-deactivate-delay", 0);
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debug("%s: base=%#08lx, periph_id=%d, max-frequency=%d, deactivate_delay=%d\n",
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__func__, plat->base, plat->periph_id, plat->frequency,
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plat->deactivate_delay_us);
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return 0;
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}
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static int tegra114_spi_probe(struct udevice *bus)
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{
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struct tegra_spi_platdata *plat = dev_get_platdata(bus);
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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priv->regs = (struct spi_regs *)plat->base;
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priv->last_transaction_us = timer_get_us();
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priv->freq = plat->frequency;
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priv->periph_id = plat->periph_id;
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return 0;
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}
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static int tegra114_spi_claim_bus(struct udevice *bus)
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{
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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/* Change SPI clock to correct frequency, PLLP_OUT0 source */
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clock_start_periph_pll(priv->periph_id, CLOCK_ID_PERIPH, priv->freq);
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/* Clear stale status here */
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setbits_le32(®s->fifo_status,
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SPI_FIFO_STS_ERR |
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SPI_FIFO_STS_TX_FIFO_OVF |
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SPI_FIFO_STS_TX_FIFO_UNR |
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SPI_FIFO_STS_RX_FIFO_OVF |
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SPI_FIFO_STS_RX_FIFO_UNR |
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SPI_FIFO_STS_TX_FIFO_FULL |
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SPI_FIFO_STS_TX_FIFO_EMPTY |
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SPI_FIFO_STS_RX_FIFO_FULL |
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SPI_FIFO_STS_RX_FIFO_EMPTY);
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debug("%s: FIFO STATUS = %08x\n", __func__, readl(®s->fifo_status));
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/* Set master mode and sw controlled CS */
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setbits_le32(®s->command1, SPI_CMD1_M_S | SPI_CMD1_CS_SW_HW |
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(priv->mode << SPI_CMD1_MODE_SHIFT));
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debug("%s: COMMAND1 = %08x\n", __func__, readl(®s->command1));
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return 0;
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}
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/**
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* Activate the CS by driving it LOW
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_activate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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/* If it's too soon to do another transaction, wait */
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if (pdata->deactivate_delay_us &&
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priv->last_transaction_us) {
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ulong delay_us; /* The delay completed so far */
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delay_us = timer_get_us() - priv->last_transaction_us;
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if (delay_us < pdata->deactivate_delay_us)
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udelay(pdata->deactivate_delay_us - delay_us);
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}
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clrbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
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}
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/**
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* Deactivate the CS by driving it HIGH
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*
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* @param slave Pointer to spi_slave to which controller has to
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* communicate with
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*/
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static void spi_cs_deactivate(struct udevice *dev)
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{
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struct udevice *bus = dev->parent;
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struct tegra_spi_platdata *pdata = dev_get_platdata(bus);
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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setbits_le32(&priv->regs->command1, SPI_CMD1_CS_SW_VAL);
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/* Remember time of this transaction so we can honour the bus delay */
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if (pdata->deactivate_delay_us)
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priv->last_transaction_us = timer_get_us();
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debug("Deactivate CS, bus '%s'\n", bus->name);
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}
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static int tegra114_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *data_out, void *data_in,
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unsigned long flags)
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{
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struct udevice *bus = dev->parent;
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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struct spi_regs *regs = priv->regs;
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u32 reg, tmpdout, tmpdin = 0;
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const u8 *dout = data_out;
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u8 *din = data_in;
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int num_bytes;
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int ret;
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debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
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__func__, bus->seq, spi_chip_select(dev), dout, din, bitlen);
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if (bitlen % 8)
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return -1;
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num_bytes = bitlen / 8;
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ret = 0;
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/* clear all error status bits */
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reg = readl(®s->fifo_status);
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writel(reg, ®s->fifo_status);
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clrsetbits_le32(®s->command1, SPI_CMD1_CS_SW_VAL,
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SPI_CMD1_RX_EN | SPI_CMD1_TX_EN | SPI_CMD1_LSBY_FE |
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(spi_chip_select(dev) << SPI_CMD1_CS_SEL_SHIFT));
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/* set xfer size to 1 block (32 bits) */
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writel(0, ®s->dma_blk);
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(dev);
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/* handle data in 32-bit chunks */
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while (num_bytes > 0) {
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int bytes;
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int tm, i;
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tmpdout = 0;
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bytes = (num_bytes > 4) ? 4 : num_bytes;
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if (dout != NULL) {
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for (i = 0; i < bytes; ++i)
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tmpdout = (tmpdout << 8) | dout[i];
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dout += bytes;
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}
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num_bytes -= bytes;
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/* clear ready bit */
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setbits_le32(®s->xfer_status, SPI_XFER_STS_RDY);
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clrsetbits_le32(®s->command1,
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SPI_CMD1_BIT_LEN_MASK << SPI_CMD1_BIT_LEN_SHIFT,
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(bytes * 8 - 1) << SPI_CMD1_BIT_LEN_SHIFT);
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writel(tmpdout, ®s->tx_fifo);
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setbits_le32(®s->command1, SPI_CMD1_GO);
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/*
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* Wait for SPI transmit FIFO to empty, or to time out.
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* The RX FIFO status will be read and cleared last
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*/
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for (tm = 0; tm < SPI_TIMEOUT; ++tm) {
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u32 fifo_status, xfer_status;
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xfer_status = readl(®s->xfer_status);
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if (!(xfer_status & SPI_XFER_STS_RDY))
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continue;
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fifo_status = readl(®s->fifo_status);
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if (fifo_status & SPI_FIFO_STS_ERR) {
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debug("%s: got a fifo error: ", __func__);
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if (fifo_status & SPI_FIFO_STS_TX_FIFO_OVF)
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debug("tx FIFO overflow ");
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if (fifo_status & SPI_FIFO_STS_TX_FIFO_UNR)
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debug("tx FIFO underrun ");
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if (fifo_status & SPI_FIFO_STS_RX_FIFO_OVF)
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debug("rx FIFO overflow ");
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if (fifo_status & SPI_FIFO_STS_RX_FIFO_UNR)
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debug("rx FIFO underrun ");
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if (fifo_status & SPI_FIFO_STS_TX_FIFO_FULL)
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debug("tx FIFO full ");
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if (fifo_status & SPI_FIFO_STS_TX_FIFO_EMPTY)
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debug("tx FIFO empty ");
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if (fifo_status & SPI_FIFO_STS_RX_FIFO_FULL)
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debug("rx FIFO full ");
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if (fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)
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debug("rx FIFO empty ");
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debug("\n");
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break;
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}
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if (!(fifo_status & SPI_FIFO_STS_RX_FIFO_EMPTY)) {
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tmpdin = readl(®s->rx_fifo);
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/* swap bytes read in */
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if (din != NULL) {
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for (i = bytes - 1; i >= 0; --i) {
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din[i] = tmpdin & 0xff;
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tmpdin >>= 8;
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}
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din += bytes;
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}
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/* We can exit when we've had both RX and TX */
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break;
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}
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}
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if (tm >= SPI_TIMEOUT)
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ret = tm;
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/* clear ACK RDY, etc. bits */
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writel(readl(®s->fifo_status), ®s->fifo_status);
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}
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(dev);
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debug("%s: transfer ended. Value=%08x, fifo_status = %08x\n",
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__func__, tmpdin, readl(®s->fifo_status));
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if (ret) {
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printf("%s: timeout during SPI transfer, tm %d\n",
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__func__, ret);
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return -1;
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}
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return ret;
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}
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static int tegra114_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct tegra_spi_platdata *plat = bus->platdata;
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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if (speed > plat->frequency)
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speed = plat->frequency;
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priv->freq = speed;
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debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
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return 0;
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}
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static int tegra114_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct tegra114_spi_priv *priv = dev_get_priv(bus);
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priv->mode = mode;
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debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
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return 0;
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}
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static const struct dm_spi_ops tegra114_spi_ops = {
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.claim_bus = tegra114_spi_claim_bus,
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.xfer = tegra114_spi_xfer,
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.set_speed = tegra114_spi_set_speed,
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.set_mode = tegra114_spi_set_mode,
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/*
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* cs_info is not needed, since we require all chip selects to be
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* in the device tree explicitly
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*/
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};
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static const struct udevice_id tegra114_spi_ids[] = {
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{ .compatible = "nvidia,tegra114-spi" },
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{ }
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};
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U_BOOT_DRIVER(tegra114_spi) = {
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.name = "tegra114_spi",
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.id = UCLASS_SPI,
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.of_match = tegra114_spi_ids,
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.ops = &tegra114_spi_ops,
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.ofdata_to_platdata = tegra114_spi_ofdata_to_platdata,
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.platdata_auto_alloc_size = sizeof(struct tegra_spi_platdata),
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.priv_auto_alloc_size = sizeof(struct tegra114_spi_priv),
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.per_child_auto_alloc_size = sizeof(struct spi_slave),
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.probe = tegra114_spi_probe,
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};
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