mirror of
https://github.com/brain-hackers/u-boot-brain
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8564acf936
- Correct flash and JFFS2 support for MPC8260ADS
- fix PVR values and clock generation for PowerQUICC II family
(8270/8275/8280)
* Patch by Bernhard Kuhn, 08 Jul 2003:
- add support for M68K targets
* Patch by Ken Chou, 3 Jul:
- Fix PCI config table for A3000
- Fix iobase for natsemi.c
(PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON
69 lines
2.3 KiB
C
69 lines
2.3 KiB
C
/*
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* (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#define VIDEO_ENCODER_NAME "Analog Devices AD7179"
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#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
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#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
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#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
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#undef VIDEO_MODE_RGB
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#define VIDEO_MODE_BPP 16
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#ifdef VIDEO_MODE_PAL
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#define VIDEO_ACTIVE_COLS 720
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#define VIDEO_ACTIVE_ROWS 576
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#define VIDEO_VISIBLE_COLS 640
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#define VIDEO_VISIBLE_ROWS 480
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#else
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#error "NTSC mode is not supported"
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#endif
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static unsigned char video_encoder_data[] = {
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0x05, /* Mode Register 0 */
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0x11, /* Mode Register 1 */
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0x20, /* Mode Register 2 */
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0x0C, /* Mode Register 3 */
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0x01, /* Mode Register 4 */
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0x00, /* Reserved */
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0x00, /* Reserved */
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0x04, /* Timing Register 0 */
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0x00, /* Timing Register 1 */
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0xCB, /* Subcarrier Frequency Register 0 */
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0x0A, /* Subcarrier Frequency Register 1 */
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0x09, /* Subcarrier Frequency Register 2 */
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0x2A, /* Subcarrier Frequency Register 3 */
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0x00, /* Subcarrier Phase */
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0x00, /* Closed Captioning Ext Reg 0 */
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0x00, /* Closed Captioning Ext Reg 1 */
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0x00, /* Closed Captioning Reg 0 */
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0x00, /* Closed Captioning Reg 1 */
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0x00, /* Pedestal Control Reg 0 */
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0x00, /* Pedestal Control Reg 1 */
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0x00, /* Pedestal Control Reg 2 */
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0x00, /* Pedestal Control Reg 3 */
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0x00, /* CGMS_WSS Reg 0 */
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0x00, /* CGMS_WSS Reg 0 */
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0x00, /* CGMS_WSS Reg 0 */
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0x00 /* Teletext Req. Control Reg */
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} ;
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