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https://github.com/brain-hackers/u-boot-brain
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a877bec3ec
This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
43 lines
904 B
C
43 lines
904 B
C
/*
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* Copyright (C) 2012 Altera Corporation <www.altera.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _RESET_MANAGER_H_
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#define _RESET_MANAGER_H_
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void reset_cpu(ulong addr);
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void reset_deassert_peripherals_handoff(void);
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void socfpga_bridges_reset(int enable);
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void socfpga_emac_reset(int enable);
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void socfpga_watchdog_reset(void);
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void socfpga_spim_enable(void);
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struct socfpga_reset_manager {
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u32 status;
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u32 ctrl;
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u32 counts;
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u32 padding1;
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u32 mpu_mod_reset;
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u32 per_mod_reset;
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u32 per2_mod_reset;
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u32 brg_mod_reset;
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};
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#if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 2
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#else
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#define RSTMGR_CTRL_SWWARMRSTREQ_LSB 1
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#endif
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#define RSTMGR_PERMODRST_EMAC0_LSB 0
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#define RSTMGR_PERMODRST_EMAC1_LSB 1
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#define RSTMGR_PERMODRST_L4WD0_LSB 6
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#define RSTMGR_PERMODRST_SPIM0_LSB 18
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#define RSTMGR_PERMODRST_SPIM1_LSB 19
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#endif /* _RESET_MANAGER_H_ */
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