mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-13 22:56:17 +09:00
de01a768f0
Each USB port corresponds to the following IP core: port0: xHCI (0x65a00000) SS+HS port1: xHCI (0x65c00000) HS (SS PHY is not implemented) port2: EHCI (0x5a800100) HS port3: EHCI (0x5a810100) HS Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
58 lines
920 B
Plaintext
58 lines
920 B
Plaintext
/*
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* Device Tree Source for UniPhier PH1-Pro4 Reference Board
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*
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* Copyright (C) 2014-2015 Panasonic Corporation
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* Author: Masahiro Yamada <yamada.m@jp.panasonic.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/dts-v1/;
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/include/ "uniphier-ph1-pro4.dtsi"
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/include/ "uniphier-ref-daughter.dtsi"
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/ {
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model = "Panasonic UniPhier PH1-Pro4 Reference Board";
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compatible = "panasonic,ph1-pro4-ref", "panasonic,ph1-pro4";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>;
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};
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chosen {
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bootargs = "console=ttyPS0,115200 earlyprintk";
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stdout-path = &uart0;
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};
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aliases {
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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i2c0 = &i2c0;
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i2c1 = &i2c1;
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i2c2 = &i2c2;
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i2c3 = &i2c3;
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i2c5 = &i2c5;
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i2c6 = &i2c6;
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usb0 = &usb0;
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};
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};
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&uart0 {
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status = "okay";
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};
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&uart1 {
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status = "okay";
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};
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&i2c0 {
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status = "okay";
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};
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&usb0 {
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status = "okay";
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};
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