mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-08 20:26:17 +09:00
83d290c56f
When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
318 lines
7.4 KiB
ArmAsm
318 lines
7.4 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2011 Andes Technology Corporation
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* Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
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* Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
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*/
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.pic
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.text
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#include <common.h>
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#include <config.h>
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#include <asm/macro.h>
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#include <generated/asm-offsets.h>
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/*
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* parameters for the SDRAM controller
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*/
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#define SDMC_TP1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP1)
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#define SDMC_TP2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_TP2)
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#define SDMC_CR1_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR1)
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#define SDMC_CR2_A (CONFIG_FTSDMC021_BASE + FTSDMC021_CR2)
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#define SDMC_B0_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK0_BSR)
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#define SDMC_B1_BSR_A (CONFIG_FTSDMC021_BASE + FTSDMC021_BANK1_BSR)
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#define SDMC_TP1_D CONFIG_SYS_FTSDMC021_TP1
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#define SDMC_TP2_D CONFIG_SYS_FTSDMC021_TP2
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#define SDMC_CR1_D CONFIG_SYS_FTSDMC021_CR1
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#define SDMC_CR2_D CONFIG_SYS_FTSDMC021_CR2
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#define SDMC_B0_BSR_D CONFIG_SYS_FTSDMC021_BANK0_BSR
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#define SDMC_B1_BSR_D CONFIG_SYS_FTSDMC021_BANK1_BSR
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/*
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* for Orca and Emerald
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*/
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#define BOARD_ID_REG 0x104
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#define BOARD_ID_FAMILY_MASK 0xfff000
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#define BOARD_ID_FAMILY_V5 0x556000
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#define BOARD_ID_FAMILY_K7 0x74b000
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/*
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* parameters for the static memory controller
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*/
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#define SMC_BANK0_CR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_CR)
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#define SMC_BANK0_TPR_A (CONFIG_FTSMC020_BASE + FTSMC020_BANK0_TPR)
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#define SMC_BANK0_CR_D FTSMC020_BANK0_LOWLV_CONFIG
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#define SMC_BANK0_TPR_D FTSMC020_BANK0_LOWLV_TIMING
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/*
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* parameters for the ahbc controller
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*/
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#define AHBC_CR_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_CR)
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#define AHBC_BSR6_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_6)
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/*
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* for Orca and Emerald
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*/
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#define AHBC_BSR4_A (CONFIG_FTAHBC020S_BASE + FTAHBC020S_SLAVE_BSR_4)
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#define AHBC_BSR6_D CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6
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/*
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* parameters for the pmu controoler
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*/
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#define PMU_PDLLCR0_A (CONFIG_FTPMU010_BASE + FTPMU010_PDLLCR0)
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/*
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* numeric 7 segment display
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*/
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.macro led, num
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write32 CONFIG_DEBUG_LED, \num
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.endm
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/*
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* Waiting for SDRAM to set up
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*/
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.macro wait_sdram
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li $r0, CONFIG_FTSDMC021_BASE
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1:
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lwi $r1, [$r0+FTSDMC021_CR2]
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bnez $r1, 1b
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.endm
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.globl mem_init
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mem_init:
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move $r11, $lp
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/*
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* mem_init:
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* There are 2 bank connected to FTSMC020 on AG101
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* BANK0: FLASH/ROM (SW5, J16), BANK1: OnBoard SDRAM.
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* we need to set onboard SDRAM before remap and relocation.
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*/
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led 0x01
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/*
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* for Orca and Emerald
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* disable write protection and reset bank size
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*/
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li $r0, SMC_BANK0_CR_A
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lwi $r1, [$r0+#0x00]
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ori $r1, $r1, 0x8f0
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xori $r1, $r1, 0x8f0
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/* check board */
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li $r3, CONFIG_FTPMU010_BASE + BOARD_ID_REG
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lwi $r3, [$r3]
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li $r4, BOARD_ID_FAMILY_MASK
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and $r3, $r3, $r4
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li $r4, BOARD_ID_FAMILY_K7
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xor $r4, $r3, $r4
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beqz $r4, use_flash_16bit_boot
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/* 32-bit mode */
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use_flash_32bit_boot:
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ori $r1, $r1, 0x50
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li $r2, 0x00151151
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j sdram_b0_cr
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/* 16-bit mode */
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use_flash_16bit_boot:
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ori $r1, $r1, 0x60
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li $r2, 0x00153153
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/* SRAM bank0 config */
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sdram_b0_cr:
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swi $r1, [$r0+#0x00]
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swi $r2, [$r0+#0x04]
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/* config AHB Controller */
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led 0x02
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/*
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* config PMU controller
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*/
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/* ftpmu010_dlldis_disable, must do it in lowleve_init */
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led 0x03
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setbf32 PMU_PDLLCR0_A, FTPMU010_PDLLCR0_DLLDIS ! 0x00010000
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/*
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* config SDRAM controller
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*/
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led 0x04
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write32 SDMC_TP1_A, SDMC_TP1_D ! 0x00011312
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led 0x05
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write32 SDMC_TP2_A, SDMC_TP2_D ! 0x00480180
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led 0x06
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write32 SDMC_CR1_A, SDMC_CR1_D ! 0x00002326
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led 0x07
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write32 SDMC_CR2_A, FTSDMC021_CR2_IPREC ! 0x00000010
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wait_sdram
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led 0x08
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write32 SDMC_CR2_A, FTSDMC021_CR2_ISMR ! 0x00000004
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wait_sdram
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led 0x09
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write32 SDMC_CR2_A, FTSDMC021_CR2_IREF ! 0x00000008
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wait_sdram
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led 0x0a
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move $lp, $r11
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ret
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#ifndef CONFIG_SKIP_LOWLEVEL_INIT
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.globl lowlevel_init
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lowlevel_init:
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move $r10, $lp
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led 0x10
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jal remap
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
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led 0x1f
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jal enable_fpu
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#endif
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led 0x20
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ret $r10
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remap:
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move $r11, $lp
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#ifdef __NDS32_N1213_43U1H__ /* NDS32 V0 ISA - AG101 Only */
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bal 2f
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relo_base:
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move $r0, $lp
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#else
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relo_base:
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mfusr $r0, $pc
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#endif /* __NDS32_N1213_43U1H__ */
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/* Remapping */
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led 0x1a
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write32 SDMC_B0_BSR_A, SDMC_B0_BSR_D ! 0x00001800
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write32 SDMC_B1_BSR_A, SDMC_B1_BSR_D ! 0x00001880
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/* clear empty BSR registers */
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led 0x1b
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li $r4, CONFIG_FTSDMC021_BASE
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li $r5, 0x0
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swi $r5, [$r4 + FTSDMC021_BANK2_BSR]
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swi $r5, [$r4 + FTSDMC021_BANK3_BSR]
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#ifdef CONFIG_MEM_REMAP
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/*
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* Copy ROM code to SDRAM base for memory remap layout.
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* This is not the real relocation, the real relocation is the function
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* relocate_code() is start.S which supports the systems is memory
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* remapped or not.
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*/
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/*
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* Doing memory remap is essential for preparing some non-OS or RTOS
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* applications.
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*
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* This is also a must on ADP-AG101 board.
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* The reason is because the ROM/FLASH circuit on PCB board.
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* AG101-A0 board has 2 jumpers MA17 and SW5 to configure which
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* ROM/FLASH is used to boot.
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*
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* When SW5 = "0101", MA17 = LO, the ROM is connected to BANK0,
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* and the FLASH is connected to BANK1.
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* When SW5 = "1010", MA17 = HI, the ROM is disabled (still at BANK0),
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* and the FLASH is connected to BANK0.
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* It will occur problem when doing flash probing if the flash is at
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* BANK0 (0x00000000) while memory remapping was skipped.
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*
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* Other board like ADP-AG101P may not enable this since there is only
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* a FLASH connected to bank0.
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*/
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led 0x11
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/*
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* for Orca and Emerald
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* read sdram base address automatically
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*/
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li $r5, AHBC_BSR6_A
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lwi $r8, [$r5]
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li $r4, 0xfff00000 /* r4 = bank6 base */
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and $r4, $r4, $r8
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la $r5, _start@GOTOFF
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la $r6, _end@GOTOFF
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1:
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lwi.p $r7, [$r5], #4
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swi.p $r7, [$r4], #4
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blt $r5, $r6, 1b
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/* set remap bit */
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/*
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* MEM remap bit is operational
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* - use it to map writeable memory at 0x00000000, in place of flash
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* - before remap: flash/rom 0x00000000, sdram: 0x10000000-0x4fffffff
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* - after remap: flash/rom 0x80000000, sdram: 0x00000000
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*/
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led 0x1c
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write32 SDMC_B0_BSR_A, 0x00001000
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write32 SDMC_B1_BSR_A, 0x00001200
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li $r5, CONFIG_SYS_TEXT_BASE /* flash base address */
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add $r11, $r11, $r5 /* add flash address offset for ret */
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add $r10, $r10, $r5
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move $lp, $r11
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setbf15 AHBC_CR_A, FTAHBC020S_CR_REMAP ! 0x1
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/*
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* for Orca and Emerald
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* extend sdram size from 256MB to 2GB
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*/
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li $r5, AHBC_BSR6_A
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lwi $r6, [$r5]
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li $r4, 0xfff0ffff
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and $r6 ,$r4, $r6
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li $r4, 0x000b0000
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or $r6, $r4, $r6
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swi $r6, [$r5]
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/*
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* for Orca and Emerald
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* extend rom base from 256MB to 2GB
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*/
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li $r4, AHBC_BSR4_A
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lwi $r5, [$r4]
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li $r6, 0xffffff
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and $r5, $r5, $r6
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li $r6, 0x80000000
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or $r5, $r5, $r6
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swi $r5, [$r4]
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#endif /* #ifdef CONFIG_MEM_REMAP */
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move $lp, $r11
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2:
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ret
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/*
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* enable_fpu:
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* Some of Andes CPU version support FPU coprocessor, if so,
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* and toolchain support FPU instruction set, we should enable it.
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*/
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#if (defined(NDS32_EXT_FPU_DP) || defined(NDS32_EXT_FPU_SP))
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enable_fpu:
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mfsr $r0, $CPU_VER /* enable FPU if it exists */
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srli $r0, $r0, 3
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andi $r0, $r0, 1
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beqz $r0, 1f /* skip if no COP */
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mfsr $r0, $FUCOP_EXIST
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srli $r0, $r0, 31
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beqz $r0, 1f /* skip if no FPU */
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mfsr $r0, $FUCOP_CTL
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ori $r0, $r0, 1
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mtsr $r0, $FUCOP_CTL
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1:
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ret
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#endif
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.globl show_led
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show_led:
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li $r8, (CONFIG_DEBUG_LED)
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swi $r7, [$r8]
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ret
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#endif /* #ifndef CONFIG_SKIP_LOWLEVEL_INIT */
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