mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-07-07 19:56:18 +09:00
43a5f0df2f
This patch adds support for A320 evaluation board from Faraday. This board uses FA526 processor by default and has 512kB and 32MB NOR flash, 64M RAM. FA526 is an ARMv4 processor and uses the ARM920T source in this patch. Signed-off-by: Po-Yu Chuang <ratbert@faraday-tech.com>
119 lines
2.4 KiB
ArmAsm
119 lines
2.4 KiB
ArmAsm
/*
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* (C) Copyright 2009 Faraday Technology
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* Po-Yu Chuang <ratbert@faraday-tech.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/macro.h>
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#include <asm/arch/ftsdmc020.h>
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/*
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* parameters for the SDRAM controller
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*/
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#define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
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#define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
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#define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
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#define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
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#define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
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#define TP0_D CONFIG_SYS_FTSDMC020_TP0
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#define TP1_D CONFIG_SYS_FTSDMC020_TP1
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#define CR_D1 FTSDMC020_CR_IPREC
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#define CR_D2 FTSDMC020_CR_ISMR
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#define CR_D3 FTSDMC020_CR_IREF
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#define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
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FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
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#define ACR_D FTSDMC020_ACR_TOC(0x18)
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/*
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* numeric 7 segment display
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*/
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.macro led, num
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write32 CONFIG_DEBUG_LED, \num
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.endm
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/*
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* Waiting for SDRAM to set up
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*/
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.macro wait_sdram
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ldr r0, =CONFIG_FTSDMC020_BASE
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1:
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ldr r1, [r0, #FTSDMC020_OFFSET_CR]
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cmp r1, #0
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bne 1b
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.endm
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.globl lowlevel_init
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lowlevel_init:
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mov r11, lr
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led 0x0
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bl init_sdmc
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led 0x1
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/* everything is fine now */
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mov lr, r11
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mov pc, lr
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/*
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* memory initialization
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*/
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init_sdmc:
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led 0x10
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/* set SDRAM register */
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write32 TP0_A, TP0_D
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led 0x11
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write32 TP1_A, TP1_D
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led 0x12
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/* set to precharge */
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write32 CR_A, CR_D1
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led 0x13
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wait_sdram
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led 0x14
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/* set mode register */
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write32 CR_A, CR_D2
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led 0x15
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wait_sdram
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led 0x16
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/* set to refresh */
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write32 CR_A, CR_D3
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led 0x17
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wait_sdram
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led 0x18
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write32 B0_BSR_A, B0_BSR_D
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led 0x19
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write32 ACR_A, ACR_D
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led 0x1a
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mov pc, lr
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