mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-25 19:38:52 +09:00
228 lines
6.5 KiB
C
228 lines
6.5 KiB
C
/*
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* (C) Copyright 2007
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* Heiko Schocher, DENX Software Engineering, hs@denx.de.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#if 0
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#define DEBUG
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#endif
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#include <common.h>
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#include <mpc8xx.h>
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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#include <libfdt.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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const uint sdram_table[] =
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{
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x0ff77c00,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x08 Burst Read */
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0x0f07fc04, 0x0ffffc04, 0x00bdfc04, 0x00fffc00,
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0x00fffc00, 0x00fffc00, 0x0ff77c00, 0x1ffffc05,
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/* 0x10 Load mode register */
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0x0ffffc34, 0x0ff57c04, 0x0ffffc04, 0x1ffffc05,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x18 Single Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c04, 0x0ffffc04,
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0x0ff77c04, 0x1ffffc05, 0xfffffc04, 0xfffffc04,
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/* 0x20 Burst Write */
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0x0f07fc04, 0x0ffffc00, 0x00bd7c00, 0x00fffc00,
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0x00fffc00, 0x00fffc04, 0x0ffffc04, 0x0ff77c04,
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0x1ffffc05, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x30 Precharge all and Refresh */
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0x0ff77c04, 0x0ffffc04, 0x0ff5fc84, 0x0ffffc04,
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0x0ffffc04, 0x0ffffc84, 0x1ffffc05, 0xfffffc04,
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0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
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/* 0x3C Exception */
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0x7ffffc04, 0xfffffc07, 0xfffffc04, 0xfffffc04,
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};
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int checkboard (void)
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{
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puts ("Board: Keymile mgsuvd\n");
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return (0);
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}
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phys_size_t initdram (int board_type)
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{
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volatile immap_t *immap = (immap_t *) CFG_IMMR;
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volatile memctl8xx_t *memctl = &immap->im_memctl;
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long int size;
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upmconfig (UPMB, (uint *) sdram_table,
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sizeof (sdram_table) / sizeof (uint));
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/*
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* Preliminary prescaler for refresh (depends on number of
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* banks): This value is selected for four cycles every 62.4 us
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* with two SDRAM banks or four cycles every 31.2 us with one
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* bank. It will be adjusted after memory sizing.
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*/
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memctl->memc_mptpr = CFG_MPTPR;
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/*
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* The following value is used as an address (i.e. opcode) for
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* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
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* the port size is 32bit the SDRAM does NOT "see" the lower two
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* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
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* MICRON SDRAMs:
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* -> 0 00 010 0 010
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* | | | | +- Burst Length = 4
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* | | | +----- Burst Type = Sequential
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* | | +------- CAS Latency = 2
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* | +----------- Operating Mode = Standard
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* +-------------- Write Burst Mode = Programmed Burst Length
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*/
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memctl->memc_mar = CFG_MAR;
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/*
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* Map controller banks 1 to the SDRAM banks 1 at
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* preliminary addresses - these have to be modified after the
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* SDRAM size has been determined.
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*/
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memctl->memc_or1 = CFG_OR1_PRELIM;
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memctl->memc_br1 = CFG_BR1_PRELIM;
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memctl->memc_mbmr = CFG_MBMR & (~(MBMR_PTBE)); /* no refresh yet */
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udelay (200);
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/* perform SDRAM initializsation sequence */
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memctl->memc_mcr = 0x80802830; /* SDRAM bank 0 */
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udelay (1);
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memctl->memc_mcr = 0x80802110; /* SDRAM bank 0 - execute twice */
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udelay (1);
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memctl->memc_mbmr |= MBMR_PTBE; /* enable refresh */
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udelay (1000);
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/*
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* Check Bank 0 Memory Size for re-configuration
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*
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*/
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size = get_ram_size(SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
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udelay (1000);
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debug ("SDRAM Bank 0: %ld MB\n", size >> 20);
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return (size);
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}
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/*
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* Early board initalization.
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*/
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int board_early_init_r(void)
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{
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/* setup the UPIOx */
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*(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
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*(char *)(CFG_PIGGY_BASE + 0x03) = 0x35;
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return 0;
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}
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#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT)
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/*
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* update "memory" property in the blob
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*/
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void ft_blob_update(void *blob, bd_t *bd)
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{
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int ret, nodeoffset = 0;
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ulong brg_data[1] = {0};
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ulong memory_data[2] = {0};
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ulong flash_data[4] = {0};
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memory_data[0] = cpu_to_be32(bd->bi_memstart);
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memory_data[1] = cpu_to_be32(bd->bi_memsize);
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nodeoffset = fdt_path_offset (blob, "/memory");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "reg", memory_data,
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sizeof(memory_data));
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if (ret < 0)
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printf("ft_blob_update(): cannot set /memory/reg "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /memory node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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flash_data[2] = cpu_to_be32(bd->bi_flashstart);
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flash_data[3] = cpu_to_be32(bd->bi_flashsize);
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nodeoffset = fdt_path_offset (blob, "/localbus");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data,
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sizeof(flash_data));
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if (ret < 0)
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printf("ft_blob_update(): cannot set /localbus/ranges "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /localbus node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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/* BRG */
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brg_data[0] = cpu_to_be32(bd->bi_busfreq);
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nodeoffset = fdt_path_offset (blob, "/soc/cpm");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "brg-frequency", brg_data,
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sizeof(brg_data));
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if (ret < 0)
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printf("ft_blob_update(): cannot set /soc/cpm/brg-frequency "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /soc/cpm node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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/* MAC Adresse */
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nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet");
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if (nodeoffset >= 0) {
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ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr,
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sizeof(uchar) * 6);
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if (ret < 0)
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printf("ft_blob_update(): cannot set /soc/cpm/scc/mac-address "
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"property err:%s\n", fdt_strerror(ret));
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}
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else {
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/* memory node is required in dts */
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printf("ft_blob_update(): cannot find /soc/cpm/ethernet node "
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"err:%s\n", fdt_strerror(nodeoffset));
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}
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}
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void ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup( blob, bd);
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ft_blob_update(blob, bd);
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}
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#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */
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