mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-28 23:50:26 +09:00
2fcf033d36
Move the axp-gpio code out of the drivers/power/axp*.c code, and into a new separate axpi-gpio driver. This change drops supports for the gpio3 pin on the axp209, as that requires special handling, and no boards are using it. Besides cleaning things up by moving the code to a separate driver, as a bonus this change also adds support for the (non vusb) gpio pins on the axp221 and the gpio pins on the axp152. The new axp-gpio driver gets its own Kconfig option, and is only enabled on boards which need it. Besides that it only gets enabled in the regular u-boot build and not for the SPL as we never need it in the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
148 lines
3.0 KiB
C
148 lines
3.0 KiB
C
/*
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* (C) Copyright 2015 Hans de Goede <hdegoede@redhat.com>
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*
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* X-Powers AXP Power Management ICs gpio driver
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/pmic_bus.h>
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#include <errno.h>
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#ifdef CONFIG_AXP152_POWER
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#include <axp152.h>
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#elif defined CONFIG_AXP209_POWER
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#include <axp209.h>
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#elif defined CONFIG_AXP221_POWER
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#include <axp221.h>
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#else
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#error Unknown AXP model
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#endif
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static u8 axp_get_gpio_ctrl_reg(unsigned pin)
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{
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switch (pin) {
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case 0: return AXP_GPIO0_CTRL;
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case 1: return AXP_GPIO1_CTRL;
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#ifdef AXP_GPIO2_CTRL
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case 2: return AXP_GPIO2_CTRL;
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#endif
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#ifdef AXP_GPIO3_CTRL
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case 3: return AXP_GPIO3_CTRL;
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#endif
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}
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return 0;
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}
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int axp_gpio_direction_input(struct udevice *dev, unsigned pin)
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{
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u8 reg;
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switch (pin) {
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#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
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case SUNXI_GPIO_AXP0_VBUS_DETECT:
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return 0;
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return pmic_bus_write(reg, AXP_GPIO_CTRL_INPUT);
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}
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}
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int axp_gpio_direction_output(struct udevice *dev, unsigned pin, int val)
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{
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__maybe_unused int ret;
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u8 reg;
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switch (pin) {
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#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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ret = pmic_bus_clrbits(AXP221_MISC_CTRL,
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AXP221_MISC_CTRL_N_VBUSEN_FUNC);
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if (ret)
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return ret;
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return axp_gpio_set_value(dev, pin, val);
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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}
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int axp_gpio_get_value(struct udevice *dev, unsigned pin)
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{
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u8 reg, val, mask;
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int ret;
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switch (pin) {
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#ifndef CONFIG_AXP152_POWER /* NA on axp152 */
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case SUNXI_GPIO_AXP0_VBUS_DETECT:
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ret = pmic_bus_read(AXP_POWER_STATUS, &val);
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mask = AXP_POWER_STATUS_VBUS_PRESENT;
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break;
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#endif
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#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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ret = pmic_bus_read(AXP221_VBUS_IPSOUT, &val);
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mask = AXP221_VBUS_IPSOUT_DRIVEBUS;
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break;
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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ret = pmic_bus_read(AXP_GPIO_STATE, &val);
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mask = 1 << (pin + AXP_GPIO_STATE_OFFSET);
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}
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if (ret)
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return ret;
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return (val & mask) ? 1 : 0;
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}
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int axp_gpio_set_value(struct udevice *dev, unsigned pin, int val)
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{
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u8 reg;
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switch (pin) {
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#ifdef CONFIG_AXP221_POWER /* Only available on axp221/axp223 */
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case SUNXI_GPIO_AXP0_VBUS_ENABLE:
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if (val)
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return pmic_bus_setbits(AXP221_VBUS_IPSOUT,
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AXP221_VBUS_IPSOUT_DRIVEBUS);
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else
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return pmic_bus_clrbits(AXP221_VBUS_IPSOUT,
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AXP221_VBUS_IPSOUT_DRIVEBUS);
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#endif
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default:
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reg = axp_get_gpio_ctrl_reg(pin);
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if (reg == 0)
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return -EINVAL;
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return pmic_bus_write(reg, val ? AXP_GPIO_CTRL_OUTPUT_HIGH :
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AXP_GPIO_CTRL_OUTPUT_LOW);
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}
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}
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int axp_gpio_init(void)
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{
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int ret;
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ret = pmic_bus_init();
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if (ret)
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return ret;
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return 0;
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}
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