mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-08-20 17:08:52 +09:00
![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
304 lines
7.2 KiB
C
304 lines
7.2 KiB
C
/*
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* Copyright 2009-2011 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <command.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <miiphy.h>
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#include <libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <vsc7385.h>
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#include <netdev.h>
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#include <rtc.h>
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#include <i2c.h>
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#include <hwconfig.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define VSC7385_RST_SET 0x00080000
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#define SLIC_RST_SET 0x00040000
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#define SGMII_PHY_RST_SET 0x00020000
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#define PCIE_RST_SET 0x00010000
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#define RGMII_PHY_RST_SET 0x02000000
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#define USB_RST_CLR 0x04000000
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#define USB2_PORT_OUT_EN 0x01000000
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#define GPIO_DIR 0x060f0000
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#define BOARD_PERI_RST_SET VSC7385_RST_SET | SLIC_RST_SET | \
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SGMII_PHY_RST_SET | PCIE_RST_SET | \
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RGMII_PHY_RST_SET
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#define SYSCLK_MASK 0x00200000
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#define BOARDREV_MASK 0x10100000
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#define BOARDREV_C 0x00100000
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#define BOARDREV_D 0x00000000
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#define SYSCLK_66 66666666
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#define SYSCLK_100 100000000
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unsigned long get_board_sys_clk(ulong dummy)
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{
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volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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u32 val_gpdat, sysclk_gpio;
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val_gpdat = in_be32(&pgpio->gpdat);
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sysclk_gpio = val_gpdat & SYSCLK_MASK;
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if(sysclk_gpio == 0)
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return SYSCLK_66;
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else
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return SYSCLK_100;
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return 0;
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}
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#ifdef CONFIG_MMC
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int board_early_init_f (void)
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{
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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return 0;
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}
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#endif
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int checkboard (void)
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{
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u32 val_gpdat, board_rev_gpio;
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volatile ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
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char board_rev = 0;
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struct cpu_type *cpu;
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val_gpdat = in_be32(&pgpio->gpdat);
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board_rev_gpio = val_gpdat & BOARDREV_MASK;
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if (board_rev_gpio == BOARDREV_C)
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board_rev = 'C';
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else if (board_rev_gpio == BOARDREV_D)
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board_rev = 'D';
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else
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panic ("Unexpected Board REV %x detected!!\n", board_rev_gpio);
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cpu = gd->arch.cpu;
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printf ("Board: %sRDB Rev%c\n", cpu->name, board_rev);
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setbits_be32(&pgpio->gpdir, GPIO_DIR);
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/*
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* Bringing the following peripherals out of reset via GPIOs
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* 0 = reset and 1 = out of reset
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* GPIO12 - Reset to Ethernet Switch
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* GPIO13 - Reset to SLIC/SLAC devices
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* GPIO14 - Reset to SGMII_PHY_N
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* GPIO15 - Reset to PCIe slots
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* GPIO6 - Reset to RGMII PHY
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* GPIO5 - Reset to USB3300 devices 1 = reset and 0 = out of reset
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*/
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clrsetbits_be32(&pgpio->gpdat, USB_RST_CLR, BOARD_PERI_RST_SET);
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return 0;
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}
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int misc_init_r(void)
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{
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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ccsr_gpio_t *gpio = (void *)CONFIG_SYS_MPC85xx_GPIO_ADDR;
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setbits_be32(&gpio->gpdir, USB2_PORT_OUT_EN);
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setbits_be32(&gpio->gpdat, USB2_PORT_OUT_EN);
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_ELBC_OFF_USB2_ON);
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#endif
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return 0;
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}
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int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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unsigned int orig_bus = i2c_get_bus_num();
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u8 i2c_data;
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i2c_set_bus_num(1);
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if (i2c_read(CONFIG_SYS_I2C_PCA9557_ADDR, 0,
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1, &i2c_data, sizeof(i2c_data)) == 0) {
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if (i2c_data & 0x2)
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puts("NOR Flash Bank : Secondary\n");
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else
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puts("NOR Flash Bank : Primary\n");
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if (i2c_data & 0x1) {
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setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
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puts("SD/MMC : 8-bit Mode\n");
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puts("eSPI : Disabled\n");
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} else {
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puts("SD/MMC : 4-bit Mode\n");
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puts("eSPI : Enabled\n");
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}
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} else {
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puts("Failed reading I2C Chip 0x18 on bus 1\n");
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}
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i2c_set_bus_num(orig_bus);
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/*
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* Remap Boot flash region to caching-inhibited
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* so that flash can be erased properly.
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*/
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/* Flush d-cache and invalidate i-cache of any FLASH data */
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flush_dcache();
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invalidate_icache();
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if (flash_esel == -1) {
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/* very unlikely unless something is messed up */
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puts("Error: Could not find TLB for FLASH BASE\n");
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flash_esel = 2; /* give our best effort to continue */
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} else {
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/* invalidate existing TLB entry for flash */
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disable_tlb(flash_esel);
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}
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
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0, flash_esel, BOOKE_PAGESZ_16M, 1);
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rtc_reset();
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return 0;
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}
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#ifdef CONFIG_TSEC_ENET
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int board_eth_init(bd_t *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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struct tsec_info_struct tsec_info[4];
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int num = 0;
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char *tmp;
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unsigned int vscfw_addr;
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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num++;
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#endif
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#ifdef CONFIG_TSEC2
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SET_STD_TSEC_INFO(tsec_info[num], 2);
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num++;
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#endif
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#ifdef CONFIG_TSEC3
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SET_STD_TSEC_INFO(tsec_info[num], 3);
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if (is_serdes_configured(SGMII_TSEC3)) {
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puts("eTSEC3 is in sgmii mode.\n");
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tsec_info[num].flags |= TSEC_SGMII;
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}
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num++;
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#endif
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if (!num) {
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printf("No TSECs initialized\n");
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return 0;
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}
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#ifdef CONFIG_VSC7385_ENET
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/* If a VSC7385 microcode image is present, then upload it. */
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if ((tmp = getenv ("vscfw_addr")) != NULL) {
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vscfw_addr = simple_strtoul (tmp, NULL, 16);
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printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
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if (vsc7385_upload_firmware((void *) vscfw_addr,
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CONFIG_VSC7385_IMAGE_SIZE))
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puts("Failure uploading VSC7385 microcode.\n");
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} else
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puts("No address specified for VSC7385 microcode.\n");
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#endif
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mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
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mdio_info.name = DEFAULT_MII_NAME;
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fsl_pq_mdio_init(bis, &mdio_info);
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tsec_eth_init(bis, tsec_info, num);
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return pci_eth_init(bis);
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}
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#endif
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#if defined(CONFIG_OF_BOARD_SETUP)
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extern void ft_pci_board_setup(void *blob);
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int ft_board_setup(void *blob, bd_t *bd)
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{
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const char *soc_usb_compat = "fsl-usb2-dr";
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int err, usb1_off, usb2_off;
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phys_addr_t base;
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phys_size_t size;
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ft_cpu_setup(blob, bd);
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base = getenv_bootm_low();
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size = getenv_bootm_size();
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#if defined(CONFIG_PCI)
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ft_pci_board_setup(blob);
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#endif /* #if defined(CONFIG_PCI) */
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fdt_fixup_memory(blob, (u64)base, (u64)size);
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#if defined(CONFIG_HAS_FSL_DR_USB)
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fdt_fixup_dr_usb(blob, bd);
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#endif
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#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
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/* Delete eLBC node as it is muxed with USB2 controller */
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if (hwconfig("usb2")) {
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const char *soc_elbc_compat = "fsl,p1020-elbc";
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int off = fdt_node_offset_by_compatible(blob, -1,
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soc_elbc_compat);
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if (off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_elbc_compat);
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return off;
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}
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err = fdt_del_node(blob, off);
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if (err < 0) {
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printf("WARNING: could not remove %s\n",
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soc_elbc_compat);
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return err;
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}
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return 0;
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}
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#endif
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/* Delete USB2 node as it is muxed with eLBC */
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usb1_off = fdt_node_offset_by_compatible(blob, -1,
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soc_usb_compat);
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if (usb1_off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_usb_compat);
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return usb1_off;
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}
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usb2_off = fdt_node_offset_by_compatible(blob, usb1_off,
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soc_usb_compat);
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if (usb2_off < 0) {
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printf("WARNING: could not find compatible node %s\n",
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soc_usb_compat);
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return usb2_off;
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}
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err = fdt_del_node(blob, usb2_off);
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if (err < 0) {
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printf("WARNING: could not remove %s\n", soc_usb_compat);
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return err;
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}
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return 0;
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}
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#endif
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