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https://github.com/brain-hackers/u-boot-brain
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![Simon Glass](/assets/img/avatar_default.png)
This function can fail if the device tree runs out of space. Rather than silently booting with an incomplete device tree, allow the failure to be detected. Unfortunately this involves changing a lot of places in the code. I have not changed behvaiour to return an error where one is not currently returned, to avoid unexpected breakage. Eventually it would be nice to allow boards to register functions to be called to update the device tree. This would avoid all the many functions to do this. However it's not clear yet if this should be done using driver model or with a linker list. This work is left for later. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
223 lines
5.7 KiB
C
223 lines
5.7 KiB
C
/*
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* Copyright (C) 2007 Freescale Semiconductor, Inc.
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*
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* Michael Barkowski <michael.barkowski@freescale.com>
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* Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*/
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#include <common.h>
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#include <ioports.h>
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#include <mpc83xx.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <command.h>
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#include <libfdt.h>
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#if defined(CONFIG_PCI)
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#include <pci.h>
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#endif
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#include <asm/mmu.h>
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* UCC3 */
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{1, 0, 1, 0, 1}, /* TxD0 */
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{1, 1, 1, 0, 1}, /* TxD1 */
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{1, 2, 1, 0, 1}, /* TxD2 */
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{1, 3, 1, 0, 1}, /* TxD3 */
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{1, 9, 1, 0, 1}, /* TxER */
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{1, 12, 1, 0, 1}, /* TxEN */
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{3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
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{1, 4, 2, 0, 1}, /* RxD0 */
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{1, 5, 2, 0, 1}, /* RxD1 */
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{1, 6, 2, 0, 1}, /* RxD2 */
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{1, 7, 2, 0, 1}, /* RxD3 */
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{1, 8, 2, 0, 1}, /* RxER */
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{1, 10, 2, 0, 1}, /* RxDV */
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{0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
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{1, 11, 2, 0, 1}, /* COL */
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{1, 13, 2, 0, 1}, /* CRS */
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/* UCC2 */
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{0, 18, 1, 0, 1}, /* TxD0 */
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{0, 19, 1, 0, 1}, /* TxD1 */
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{0, 20, 1, 0, 1}, /* TxD2 */
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{0, 21, 1, 0, 1}, /* TxD3 */
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{0, 27, 1, 0, 1}, /* TxER */
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{0, 30, 1, 0, 1}, /* TxEN */
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{3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
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{0, 22, 2, 0, 1}, /* RxD0 */
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{0, 23, 2, 0, 1}, /* RxD1 */
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{0, 24, 2, 0, 1}, /* RxD2 */
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{0, 25, 2, 0, 1}, /* RxD3 */
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{0, 26, 1, 0, 1}, /* RxER */
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{0, 28, 2, 0, 1}, /* Rx_DV */
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{3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
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{0, 29, 2, 0, 1}, /* COL */
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{0, 31, 2, 0, 1}, /* CRS */
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{3, 4, 3, 0, 2}, /* MDIO */
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{3, 5, 1, 0, 2}, /* MDC */
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{0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
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};
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int fixed_sdram(void);
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phys_size_t initdram(int board_type)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
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return -1;
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/* DDR SDRAM - Main SODIMM */
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im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
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msize = fixed_sdram();
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/* return total bus SDRAM size(bytes) -- DDR */
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return (msize * 1024 * 1024);
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}
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/*************************************************************************
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* fixed sdram init -- doesn't use serial presence detect.
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************************************************************************/
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int fixed_sdram(void)
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{
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volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
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u32 msize = 0;
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u32 ddr_size;
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u32 ddr_size_log2;
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msize = CONFIG_SYS_DDR_SIZE;
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for (ddr_size = msize << 20, ddr_size_log2 = 0;
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(ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
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if (ddr_size & 1) {
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return -1;
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}
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}
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im->sysconf.ddrlaw[0].ar =
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LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
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im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
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im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
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im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
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im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
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im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
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im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
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im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
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im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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__asm__ __volatile__ ("sync");
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udelay(200);
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im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
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__asm__ __volatile__ ("sync");
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return msize;
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}
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int checkboard(void)
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{
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puts("Board: Freescale MPC8323ERDB\n");
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return 0;
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}
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static struct pci_region pci_regions[] = {
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{
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bus_start: CONFIG_SYS_PCI1_MEM_BASE,
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phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
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size: CONFIG_SYS_PCI1_MEM_SIZE,
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flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
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},
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{
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bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
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phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
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size: CONFIG_SYS_PCI1_MMIO_SIZE,
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flags: PCI_REGION_MEM
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},
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{
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bus_start: CONFIG_SYS_PCI1_IO_BASE,
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phys_start: CONFIG_SYS_PCI1_IO_PHYS,
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size: CONFIG_SYS_PCI1_IO_SIZE,
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flags: PCI_REGION_IO
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}
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};
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void pci_init_board(void)
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{
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volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
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volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
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volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
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struct pci_region *reg[] = { pci_regions };
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/* Enable all 3 PCI_CLK_OUTPUTs. */
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clk->occr |= 0xe0000000;
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/* Configure PCI Local Access Windows */
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pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
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pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
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pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
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pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
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mpc83xx_pci_init(1, reg);
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}
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#if defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, bd_t *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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#endif
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#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
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int mac_read_from_eeprom(void)
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{
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uchar buf[28];
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char str[18];
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int i = 0;
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unsigned int crc = 0;
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unsigned char enetvar[32];
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/* Read MAC addresses from EEPROM */
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if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
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printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
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CONFIG_SYS_I2C_EEPROM_ADDR);
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} else {
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uint32_t crc_buf;
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memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
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if (crc32(crc, buf, 24) == crc_buf) {
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printf("Reading MAC from EEPROM\n");
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for (i = 0; i < 4; i++) {
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if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
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sprintf(str,
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"%02X:%02X:%02X:%02X:%02X:%02X",
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buf[i * 6], buf[i * 6 + 1],
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buf[i * 6 + 2], buf[i * 6 + 3],
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buf[i * 6 + 4], buf[i * 6 + 5]);
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sprintf((char *)enetvar,
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i ? "eth%daddr" : "ethaddr", i);
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setenv((char *)enetvar, str);
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}
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}
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}
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}
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return 0;
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}
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#endif /* CONFIG_I2C_MAC_OFFSET */
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