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https://github.com/brain-hackers/u-boot-brain
synced 2024-08-21 01:18:52 +09:00
![Alison Wang](/assets/img/avatar_default.png)
This patch adds SD boot support for LS1021AQDS board. SPL framework is used. PBL initialize the internal RAM and copy SPL to it, then SPL initialize DDR using SPD and copy u-boot from SD card to DDR, finally SPL transfer control to u-boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
170 lines
4.1 KiB
C
170 lines
4.1 KiB
C
/*
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* Copyright 2014 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include "ddr.h"
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DECLARE_GLOBAL_DATA_PTR;
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
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ulong ddr_freq;
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if (ctrl_num > 3) {
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printf("Not supported controller number %d\n", ctrl_num);
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return;
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}
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if (!pdimm->n_ranks)
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return;
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pbsp = udimms[0];
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/* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
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* freqency and n_banks specified in board_specific_parameters table.
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*/
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ddr_freq = get_ddr_freq(0) / 1000000;
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while (pbsp->datarate_mhz_high) {
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if (pbsp->n_ranks == pdimm->n_ranks) {
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if (ddr_freq <= pbsp->datarate_mhz_high) {
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popts->clk_adjust = pbsp->clk_adjust;
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popts->wrlvl_start = pbsp->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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popts->cpo_override = pbsp->cpo_override;
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popts->write_data_delay =
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pbsp->write_data_delay;
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goto found;
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}
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pbsp_highest = pbsp;
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}
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pbsp++;
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}
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if (pbsp_highest) {
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printf("Error: board specific timing not found for %lu MT/s\n",
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ddr_freq);
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printf("Trying to use the highest speed (%u) parameters\n",
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pbsp_highest->datarate_mhz_high);
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popts->clk_adjust = pbsp_highest->clk_adjust;
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popts->wrlvl_start = pbsp_highest->wrlvl_start;
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popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
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popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
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} else {
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panic("DIMM is not supported by this board");
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}
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found:
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debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
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pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
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/* force DDR bus width to 32 bits */
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popts->data_bus_width = 1;
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popts->otf_burst_chop_en = 0;
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popts->burst_length = DDR_BL8;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 1;
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/*
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* Write leveling override
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*/
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popts->wrlvl_override = 1;
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popts->wrlvl_sample = 0xf;
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/*
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* Rtt and Rtt_WR override
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*/
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popts->rtt_override = 0;
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/* Enable ZQ calibration */
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popts->zq_en = 1;
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#ifdef CONFIG_SYS_FSL_DDR4
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
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DDR_CDR2_VREF_OVRD(70); /* Vref = 70% */
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#else
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popts->cswl_override = DDR_CSWL_CS0;
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/* DHC_EN =1, ODT = 75 Ohm */
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popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_75ohm);
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popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_75ohm);
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#endif
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}
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 1073741824u,
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.capacity = 1073741824u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 0,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 15,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 0,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1071,
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.caslat_x = 0xfe << 4, /* 5,6,7,8 */
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.taa_ps = 13125,
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.twr_ps = 15000,
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.trcd_ps = 13125,
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.trrd_ps = 7500,
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.trp_ps = 13125,
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.tras_ps = 37500,
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.trc_ps = 50625,
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.trfc_ps = 160000,
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.twtr_ps = 7500,
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.trtp_ps = 7500,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 37500,
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};
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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static const char dimm_model[] = "Fixed DDR on board";
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if (((controller_number == 0) && (dimm_number == 0)) ||
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((controller_number == 1) && (dimm_number == 0))) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#endif
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phys_size_t initdram(int board_type)
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{
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phys_size_t dram_size;
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#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_SPL)
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puts("Initializing DDR....using SPD\n");
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dram_size = fsl_ddr_sdram();
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#else
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dram_size = fsl_ddr_sdram_size();
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#endif
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return dram_size;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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