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![York Sun](/assets/img/avatar_default.png)
Fix the license header introduced by the following patches Add TWR-P10xx board support Add T4240EMU target IDT8T49N222A configuration code Add C29x SoC support Add support for C29XPCIE board Signed-off-by: York Sun <yorksun@freescale.com>
208 lines
5.6 KiB
C
208 lines
5.6 KiB
C
/*
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* Copyright 2013 Freescale Semiconductor, Inc.
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* Author: Shaveta Leekha <shaveta@freescale.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include "idt8t49n222a_serdes_clk.h"
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#define DEVICE_ID_REG 0x00
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static int check_pll_status(u8 idt_addr)
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{
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u8 val = 0;
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int ret;
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ret = i2c_read(idt_addr, 0x17, 1, &val, 1);
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if (ret < 0) {
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printf("IDT:0x%x could not read status register from device.\n",
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idt_addr);
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return ret;
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}
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if (val & 0x04) {
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debug("idt8t49n222a PLL is LOCKED: %x\n", val);
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} else {
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printf("idt8t49n222a PLL is not LOCKED: %x\n", val);
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return -1;
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}
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return 0;
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}
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int set_serdes_refclk(u8 idt_addr, u8 serdes_num,
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enum serdes_refclk refclk1,
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enum serdes_refclk refclk2, u8 feedback)
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{
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u8 dev_id = 0;
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int i, ret;
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debug("IDT:Configuring idt8t49n222a device at I2C address: 0x%2x\n",
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idt_addr);
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ret = i2c_read(idt_addr, DEVICE_ID_REG, 1, &dev_id, 1);
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if (ret < 0) {
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debug("IDT:0x%x could not read DEV_ID from device.\n",
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idt_addr);
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return ret;
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}
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if ((dev_id != 0x00) && (dev_id != 0x24) && (dev_id != 0x2a)) {
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debug("IDT: device at address 0x%x is not idt8t49n222a.\n",
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idt_addr);
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}
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if (serdes_num != 1 && serdes_num != 2) {
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debug("serdes_num should be 1 for SerDes1 and"
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" 2 for SerDes2.\n");
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return -1;
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}
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if ((refclk1 == SERDES_REFCLK_122_88 && refclk2 != SERDES_REFCLK_122_88)
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|| (refclk1 != SERDES_REFCLK_122_88
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&& refclk2 == SERDES_REFCLK_122_88)) {
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debug("Only one refclk at 122.88MHz is not supported."
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" Please set both refclk1 & refclk2 to 122.88MHz"
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" or both not to 122.88MHz.\n");
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return -1;
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}
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if (refclk1 != SERDES_REFCLK_100 && refclk1 != SERDES_REFCLK_122_88
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&& refclk1 != SERDES_REFCLK_125
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&& refclk1 != SERDES_REFCLK_156_25) {
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debug("refclk1 should be 100MHZ, 122.88MHz, 125MHz"
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" or 156.25MHz.\n");
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return -1;
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}
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if (refclk2 != SERDES_REFCLK_100 && refclk2 != SERDES_REFCLK_122_88
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&& refclk2 != SERDES_REFCLK_125
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&& refclk2 != SERDES_REFCLK_156_25) {
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debug("refclk2 should be 100MHZ, 122.88MHz, 125MHz"
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" or 156.25MHz.\n");
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return -1;
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}
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if (feedback != 0 && feedback != 1) {
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debug("valid values for feedback are 0(default) or 1.\n");
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return -1;
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 122.88MHz Refclk2 = 122.88MHz
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*/
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if (refclk1 == SERDES_REFCLK_122_88 &&
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refclk2 == SERDES_REFCLK_122_88) {
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printf("Setting refclk1:122.88 and refclk2:122.88\n");
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for (i = 0; i < NUM_IDT_REGS; i++)
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i2c_reg_write(idt_addr, idt_conf_122_88[i][0],
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idt_conf_122_88[i][1]);
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if (feedback) {
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for (i = 0; i < NUM_IDT_REGS_FEEDBACK; i++)
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i2c_reg_write(idt_addr,
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idt_conf_122_88_feedback[i][0],
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idt_conf_122_88_feedback[i][1]);
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}
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}
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if (refclk1 != SERDES_REFCLK_122_88 &&
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refclk2 != SERDES_REFCLK_122_88) {
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for (i = 0; i < NUM_IDT_REGS; i++)
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i2c_reg_write(idt_addr, idt_conf_not_122_88[i][0],
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idt_conf_not_122_88[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 100MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_100 && refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:100 and refclk2:125\n");
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i2c_reg_write(idt_addr, 0x11, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:125 and refclk2:125\n");
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i2c_reg_write(idt_addr, 0x10, 0x10);
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i2c_reg_write(idt_addr, 0x11, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 100MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 && refclk2 == SERDES_REFCLK_100) {
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printf("Setting refclk1:125 and refclk2:100\n");
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i2c_reg_write(idt_addr, 0x10, 0x10);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:156.25 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25[i][0],
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idt_conf_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 100MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_100 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:100 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_100_156_25[i][0],
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idt_conf_100_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 125MHz Refclk2 = 156.25MHz
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*/
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if (refclk1 == SERDES_REFCLK_125 &&
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refclk2 == SERDES_REFCLK_156_25) {
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printf("Setting refclk1:125 and refclk2:156.25\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_125_156_25[i][0],
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idt_conf_125_156_25[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 100MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_100) {
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printf("Setting refclk1:156.25 and refclk2:100\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25_100[i][0],
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idt_conf_156_25_100[i][1]);
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}
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/* Configuring IDT for output refclks as
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* Refclk1 = 156.25MHz Refclk2 = 125MHz
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*/
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if (refclk1 == SERDES_REFCLK_156_25 &&
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refclk2 == SERDES_REFCLK_125) {
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printf("Setting refclk1:156.25 and refclk2:125\n");
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for (i = 0; i < NUM_IDT_REGS_156_25; i++)
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i2c_reg_write(idt_addr, idt_conf_156_25_125[i][0],
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idt_conf_156_25_125[i][1]);
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}
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/* waiting for maximum of 1 second if PLL doesn'r get locked
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* initially. then check the status again.
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*/
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if (check_pll_status(idt_addr)) {
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mdelay(1000);
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if (check_pll_status(idt_addr))
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return -1;
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}
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return 0;
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}
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