Jean-Jacques Hiblot 2faa1a302b mmc: omap_hsmmc: Workaround for errata id i802 ... According to errata i802, DCRC error interrupts (MMCHS_STAT[21] DCRC=0x1) can occur during the tuning procedure. The DCRC interrupt, occurs when the last tuning block fails (the last ratio tested). The delay from CRC check until the interrupt is asserted is bigger than the delay until assertion of the tuning end flag. Assertion of tuning end flag is what masks the interrupts. Because of this race, an erroneous DCRC interrupt occurs. The suggested workaround is to disable DCRC interrupts during the tuning procedure which is implemented here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>		2018-02-19 16:58:54 +09:00
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asm	mmc: omap_hsmmc: Workaround for errata id i802	2018-02-19 16:58:54 +09:00
debug	arm: debug: replace license blocks with SPDX	2014-10-26 22:22:09 +01:00